Abstract: A field effect transistor includes an exposed channel region disposed between a source region and a drain region. A gate electrode is disposed over the exposed channel region. An electrolyte gel is disposed between the gate electrode and the exposed channel region, wherein ions are immobilized in the electrolyte gel below a transition temperature and mobilized above the transition temperature to increase device resistance.

Abstract: Chemical sensors and methods of forming and making the same include a semiconductor substrate having an input terminal and an output terminal. A negative capacitance structure is positioned on the semiconductor substrate and is configured to control a current passing from the input terminal to the output terminal. A functionalized electrode is in electrical contact with the negative capacitance structure and is configured to change surface potential in the presence of an analyte, such that a phase change in the negative capacitance structure is triggered when the surface potential exceeds a threshold.

Abstract: A method for forming nanoparticles includes forming a stack of alternating layers including a first material disposed between a second material. The stack of alternating layers is patterned to form pillars. A dielectric layer is conformally deposited over the pillars. The pillars are annealed in an oxygen environment to modify a shape of the first material of the alternating layers. The dielectric layer and the second material are etched selectively to the first material to form nanoparticles from the first material.

Abstract: An integrated circuit includes an array of devices with a logic pattern to implement a physically unclonable function (PUF) for chip authentication. The logic pattern is determined in accordance with processing variations during the manufacturing. The array of devices includes one or more components having a first state and one or more components having a second state. A combination of the first and second states provides the logic pattern.

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

Abstract: Embodiments of the invention are directed to a system for detecting neurotransmitters. A non-limiting example of the system includes a porous electrode. A system can also include a pH sensor attached to the porous electrode, wherein the pH sensor includes a sensing electrode and a reference electrode. The system can also include electronic circuitry in communication with the pH sensor.

Abstract: Chemical sensors and methods of forming and making the same include an input terminal and an output terminal. A negative capacitance structure is configured to control a current passing horizontally from the input terminal to the output terminal, and has a first and second metal layer that are arranged vertically with respect to one another, and a ferroelectric layer positioned between the first and second metal layers. An electrode is in electrical contact with the negative capacitance structure, and is configured to change potential, to exceed a threshold, thereby triggering a discontinuous polarization change in the negative capacitance structure.

Abstract: A method and an apparatus are provided. The apparatus includes a three-dimensional semiconductor structure having a spherical array of fixed-position optoelectronic devices arranged over a relaxed elastomer by a controlled unbuckling process that orients the fixed-position optoelectronic devices to face in different directions in the spherical array to communicate in the different directions without motion of the apparatus and the fixed-position optoelectronic devices of the apparatus.

Abstract: A method is presented for constructing conductive bridging random access memory (CBRAM) stacks. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a CBRAM stack including at least an electrolyte layer, a conductive layer, a metal cap layer, and a top electrode such that a top end of the CBRAM stack has a smaller critical dimension than a bottom end of the CBRAM stack, forming a low-k dielectric layer over the CBRAM stack, and exposing a top surface of the CBRAM stack during a via opening.

Abstract: A three-dimensional integration of synapse circuitry is formed. One or more neuron layers each comprises a plurality of computing elements, and one or more synapse layers each comprising an array of memory elements are formed on top of the one or more neuron layers. A plurality of staggered through-silicon vias (TSVs) connect the one or more neuron layers to the one or more synapse layers and operate as communication links between one or more computing elements in the one or more neuron layers and one or more memory elements in the one or more synapse layers.

Abstract: A method is presented for constructing conductive bridging random access memory (CBRAM) stacks. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a CBRAM stack including at least an electrolyte layer, a conductive layer, a metal cap layer, and a top electrode such that a top end of the CBRAM stack has a smaller critical dimension than a bottom end of the CBRAM stack, forming a low-k dielectric layer over the CBRAM stack, and exposing a top surface of the CBRAM stack during a via opening.

Abstract: A method and an apparatus are provided. The apparatus includes a three-dimensional semiconductor structure having a spherical array of fixed-position optoelectronic devices arranged over a relaxed elastomer by a controlled unbuckling process that orients the fixed-position optoelectronic devices to face in different directions in the spherical array to communicate in the different directions without motion of the apparatus and the fixed-position optoelectronic devices of the apparatus.

Abstract: A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.

Abstract: The objective of the present disclosure is to provide a method, apparatus and system of ACK/NACK reporting for Cat-M mechanism. Here, a user equipment feeds back an ACK/NACK message to an eNB on PUSCH based on received downlink data, wherein when computing the number of resource elements occupied by the ACK/NACK message on PUSCH, the number of OFDM symbols in a guard period is ruled out. This may effectively lower the UE's PUSCH data code rate, and meanwhile enhance the eNB's decoding performance on PUSCH.

Abstract: A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.

Abstract: A nanoparticle includes a cuboid base including a semiconductor material, and a plurality of surfaces formed on the base and including a plurality of functionalities, respectively.

Abstract: The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.