Abstract: A method for forming nanoparticles includes forming a stack of alternating layers including a first material disposed between a second material. The stack of alternating layers is patterned to form pillars. A dielectric layer is conformally deposited over the pillars. The pillars are annealed in an oxygen environment to modify a shape of the first material of the alternating layers. The dielectric layer and the second material are etched selectively to the first material to form nanoparticles from the first material.

Abstract: A field effect transistor includes an exposed channel region disposed between a source region and a drain region. A gate electrode is disposed over the exposed channel region. An electrolyte gel is disposed between the gate electrode and the exposed channel region, wherein ions are immobilized in the electrolyte gel below a transition temperature and mobilized above the transition temperature to increase device resistance.

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

Abstract: A drug delivery system includes a substrate, an integrated sensor disposed on the substrate, a drug delivery element disposed on the substrate, and a control unit coupled to the integrated sensor and the drug delivery element. The integrated sensor includes first and second electrodes disposed on a first surface of the substrate. The drug delivery element includes a reservoir disposed on the first surface of the substrate, a thermally active polymer enclosing the reservoir, and a heating coil disposed over the thermally active polymer. The control unit is configured to measure a biological parameter by measuring a voltage difference between the first and second electrodes of the integrated sensor, and to apply a trigger signal to the heating coil of the drug delivery element responsive to the measured biological parameter indicating a designated condition to heat up the thermally active polymer to selectively release a drug from the reservoir.

Abstract: A method for forming nanoparticles includes forming a stack of alternating layers including a first material disposed between a second material. The stack of alternating layers is patterned to form pillars. A dielectric layer is conformally deposited over the pillars. The pillars are annealed in an oxygen environment to modify a shape of the first material of the alternating layers. The dielectric layer and the second material are etched selectively to the first material to form nanoparticles from the first material.

Abstract: Aspects include high resolution brain-electronic interfaces and related methods. Aspects include forming a semiconductor circuit on a substrate, depositing a tensile stress layer on the circuit, and separating the semiconductor circuit from a portion of the silicon substrate. Aspects also include removing the tensile stress layer from the semiconductor circuit and transferring the semiconductor circuit to a biocompatible film.

Abstract: A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.

Abstract: A magnetic trap is configured to arrange at least one diamagnetic rod. The magnetic trap includes first and second magnets on a substrate that forms the magnetic trap defining a template configured to self-assemble diamagnetic material. Each of the first and second magnets extends along a longitudinal direction to define a magnet length, and contact each other to define a contact line. The first magnet and the second magnet have a diametric magnetization in a direction perpendicular to the contact line and the longitudinal direction so as to generate a longitudinal energy potential that traps the diamagnetic rod along the longitudinal direction.

Abstract: The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.

Abstract: A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.

Abstract: A nanoparticle includes a cuboid base including a semiconductor material, and a plurality of surfaces formed on the base and including a plurality of functionalities, respectively.

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

Abstract: A method of forming a nanoparticle includes forming a layer of semiconductor material on a substrate, forming a first layer on the semiconductor material, and etching the semiconductor layer to form the nanoparticle including the first layer on a first side of the nanoparticle and the semiconductor material on a second side of the nanoparticle.

Abstract: The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.

Abstract: A method of forming a semiconductor structure includes patterning one or more fin structures disposed over a top surface of a substrate, a given one of the fin structures comprising a first semiconductor layer comprising a first material disposed over the top surface of the substrate and a second semiconductor layer comprising a second material disposed over a top surface of the first semiconductor layer. The method further includes forming a liner over the one or more fin structures, and performing an anneal process to form one or more nanoscale features in a top surface of the second semiconductor layer. The second material exhibits enhanced diffusion, relative to the first material, at an interface of the liner and sidewalls of the given fin structure.