Abstract: A camera may capture reflected light from the surface of the wafer during a semiconductor process that adds or removes material from the wafer, such as an etch process. To accurately determine an endpoint for the process, a camera sampling rate and light source intensity may be optimized in the process recipe. Optimizing the light source intensity may include characterizing light intensities that will be reflected from the waiver using an image of the wafer. Pixel intensities may be used to adjust the light source intensity to compensate for more complex wafer patterns. Optimizing the camera sampling rates may include nondestructively rotating a view of the wafer and converting the sampled intensities to the frequency domain. The camera sampling rate may be increased or decreased to remove spatial noise from the image without oversampling unnecessarily. These optimized parameters may then generate a clean, repeatable trace for endpoint determination.

Abstract: Disclosed herein are approaches for forming contacts in a 4F2 vertical dynamic random-access memory device. One method includes providing a plurality of fins extending from a substrate, forming a spacer layer over the plurality of fins, and etching the substrate to expose a base portion of the plurality of fins. The method may include forming a doped layer along the base portion of the plurality of fins and along an upper surface of the substrate, and forming an oxide spacer over the doped layer.

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

Abstract: Provided here are methods and manufacturing systems to implant protons into SiC IGBT devices at multiple depths in the drift layer of the SiC IGBT device. Provides are SiC IGBT devices manufactured with process steps including multiple proton implant processes where the SiC IGBT device is irradiated with ion to affect proton implantation into the SiC IGBT device at multiple depths in the drift region to reduced minority carrier lifetime.

Abstract: A method of promoting adhesion between a dielectric layer of a semiconductor device and a metal fill deposited within a trench in the dielectric layer, including performing an ion implantation process wherein an ion beam formed of an ionized dopant species is directed into the trench at an acute angle relative to a top surface of the dielectric layer to form an implantation layer in a sidewall of the trench, and depositing a metal fill in the trench atop an underlying bottom metal layer, wherein the metal fill adheres to the sidewall.

Abstract: Disclosed herein are approaches for forming a SiC MOSFET including at least one trench with rounded corners. In one approach, a method may include providing a masking layer over a silicon carbide (SiC) layer, wherein an opening is formed in the masking layer, and providing a sidewall spacer along a sidewall of the opening of the masking layer. The method may further include forming an implant region within the SiC layer by directing ions through the opening defined by the sidewall spacer, performing a first etch to the SiC layer, wherein the first etch forms a central recess and a set of shoulder regions adjacent the central recess, and performing a second etch to remove the set of shoulder regions.

Abstract: Disclosed herein are approaches for forming a FDSOI, single diffusion break device. In one approach, a method may include providing a plurality of gates in a stack of layers, wherein each gate of the plurality of gates comprises a sidewall spacer, and forming a mask over the stack of layers, wherein an opening through the mask exposes a dummy gate of the plurality of gates. The method may further comprise etching a gate material of the dummy gate to form a recess in a silicon-on-insulator (SOI) layer of the stack of layers, implanting oxygen ions into the recess, and annealing the SOI layer within the recess to form an isolation area.

Abstract: Disclosed herein are approaches for reducing buried channel recess depth using a non-doping ion implant prior to formation of the buried channel. In one approach, a method may include providing an oxide layer over a substrate, performing a non-doping implantation process through the oxide layer to form an amorphous region in the substrate, and forming a photoresist over the oxide layer. The method may further include forming a buried layer in the substrate by implanting the substrate through an opening in the photoresist, and performing an oxidation and dopant drive-in process to the amorphous region and to the buried layer to form a second oxide layer.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: A method may include providing a substrate, where the substrate includes a first main surface and a second main surface, opposite the first main surface. The second main surface may include a stress compensation layer. The method may include directing ions to the stress compensation layer in an ion implant procedure. The ion implant procedure may include exposing a first region of the stress compensation layer to a first implant process, wherein a second region of the stress compensation layer is not exposed to the first implant process.

Abstract: A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.

Abstract: Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.

Abstract: Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.

Abstract: A P-type field effect transistor (PFET) device and a method for fabricating a PFET device using fully depleted silicon on insulator (FDSOI) technology is disclosed. The method includes introducing germanium into the channel layer using ion implantation. This germanium implant increases the axial stress in the channel layer, improving device performance. This implant may be performed at low temperatures to minimize damage to the crystalline structure. Further, rather than using a long duration, high temperature anneal process, the germanium implanted in the channel layer may be annealed using a laser anneal or a rapid temperature anneal. The implanted regions are re-crystallized using the channel layer that is beneath the gate as the seed layer. In some embodiments, an additional oxide spacer is used to further separate the raised source and drain regions from the gate.

Abstract: Disclosed herein are approaches for reducing buried channel recess depth using a non-doping ion implant prior to formation of the buried channel. In one approach, a method may include providing an oxide layer over a substrate, performing a non-doping implantation process through the oxide layer to form an amorphous region in the substrate, and forming a photoresist over the oxide layer. The method may further include forming a buried layer in the substrate by implanting the substrate through an opening in the photoresist, and performing an oxidation and dopant drive-in process to the amorphous region and to the buried layer to form a second oxide layer.

Abstract: A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.

Abstract: A method of performing an ion implantation process using a beam-line ion implanter, including disposing a substrate on a platen, analyzing the substrate using metrology components, communicating data relating to the analysis of the substrate to a feedforward controller, processing the data using a predictive model executed by the feedforward controller to compensate for variations in the substrate and to compensate for variations in components of the beam-line ion implanter based on historical data collected from previous implantation operations, and using output from the predictive model to adjust operational parameters of the beam-line ion implanter.

Abstract: Disclosed herein are methods for backside wafer dopant activation using a high-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a high-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches.

Abstract: Disclosed herein are methods for increasing MOSFET threshold voltage to enable higher SiC mobility. In some embodiments, a method includes providing a device structure including a dielectric layer over an epitaxial layer, patterning a hardmask layer over the dielectric layer, performing a first ion implant to form a well in the epitaxial layer, and performing a second ion implant to form an interface layer between the well and the dielectric layer.