Abstract: Disclosed herein are approaches for forming contacts in a 4F2 vertical dynamic random-access memory device. One method includes forming a hardmask over a plurality of pillars and over a plurality of anchors, wherein the pillars are separated from one another by a STI, and removing the STI and etching through the hardmask to form a plurality of gate trenches. The method may further include delivering a capping material to the pillars at a non-zero angle relative to a perpendicular extending from an upper surface of the pillars, wherein the capping material forms a capping layer along an upper portion of the pillars without forming the capping layer along a lower portion of the pillars. The method may further include etching the pillars to trim the lower portion of the pillars, and forming a plurality of contacts in the upper portion of the pillars.

Abstract: A vector search method includes: obtaining a query object; obtaining, by querying a first index, N vector identifiers corresponding to the query object, where the first index is stored in a memory, N is a positive integer, the N vector identifiers include a plurality of first vector identifiers, and the first vector identifier is a vector identifier that is not determined to be recalled; determining, by querying index entries that are in a second index, second vector identifiers corresponding to the plurality of first vector identifiers, the second index is stored in a persistent storage medium, and a compression ratio of a vector in the first index is greater than that of a vector in the second index; and obtaining a query result of the query object based on the second vector identifiers.

Abstract: Disclosed herein are methods for forming MOSFET trenches using an ashable mask. In some embodiments, a method may include providing a device structure including an epitaxial layer and a hard mask over the epitaxial layer, and forming a set of trenches through the epitaxial layer, wherein each trench of the set of trenches is defined by a sidewall and a bottom surface. The method may further include forming an ashable mask over the device structure, including within each trench of the set of trenches, and forming an implanted region in the epitaxial layer, below the bottom surface of each trench, by delivering ions into the set of trenches while the ashable mask is along the sidewall and the bottom surface of each trench of the set of trenches.

Abstract: A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.

Abstract: Embodiments herein are directed to localized wafer thickness correction. In some embodiments, a method may include providing a substrate including an upper surface having a raised portion extending above a plane defined by the upper surface, and a non-raised portion adjacent the raised portion. The method may further include performing a metrology scan of the upper surface to determine a first dimension of the raised portion and a second dimension of the non-raised portion, and depositing a hardmask over the upper surface, including over the raised portion and the non-raised portion. The method may further include directing ions to the hardmask, wherein a first dose of the ions over the raised portion is greater than a second dose of the ions over the non-raised portion, and performing a first etch to the hardmask to remove the hardmask over the raised portion, wherein the hardmask remains over the non-raised portion.

Abstract: Devices and methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.

Abstract: Disclosed herein are methods for forming MOSFET trenches with improved corner properties. In some embodiments, a method may include providing a device structure including an epitaxial layer and a hard mask over the epitaxial layer, and forming a trench through the well and the epitaxial layer, wherein the trench is defined by a sidewall, a bottom, and a corner at an intersection of the sidewall and the bottom. The method may further include implanting the device structure by delivering ions into the corner and into the bottom of the trench, and etching the trench to increase rounding of the corner.

Abstract: Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.

Abstract: Disclosed herein are approaches for adjusting local refractive index for photonics IC systems using selective waveguide ion implantation. In one approach, a method may include depositing an optical device film atop a base layer, patterning the optical device film into a plurality of sections, and implanting a first section of the plurality of sections of the optical device film to adjust a refractive index of the first section.

Abstract: Disclosed herein are approaches for creating high electron mobility transistors with reduced contact resistance. In one approach, a method of forming a semiconductor device may include applying a first patterned mask on top of layered stack, wherein the layered stack includes a substrate, a buffer layer disposed over the substrate, a channel layer disposed above the buffer layer, and a barrier layer disposed above the channel layer. The method may further include forming, through an opening of the patterned mask, a source/drain contact in the barrier layer by delivering a first implant to the layered stack, and performing an etch process to form a contact opening in the source/drain contact. The method may further include performing a second implant to the source/drain contact, wherein the second implant is directed into the contact opening.

Abstract: Disclosed herein are methods for forming a buried layer using a low-temperature ion implant. In some embodiments a method may include providing an opening through a mask, wherein the mask is formed directly atop a substrate, and forming a buried layer in the substrate by performing a low-temperature ion implant through the opening of the mask. The method may further include forming an oxide layer over the substrate including over the buried layer.

Abstract: Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). An example DRAM device may include a plurality of pillars extending from a base of a substrate, a gate formed around the plurality of pillars, and a buried bitline formed within the base, wherein an upper surface of the buried bitline is recessed below an upper surface of the base. The DRAM device may further include a bottom source/drain formed beneath the plurality of pillars, and a contact formed in the bottom source/drain, between the plurality of pillars.

Abstract: Disclosed are approaches for forming 4F2 vertical DRAM devices including buried bitlines. One DRAM device may include a plurality of bitlines between a plurality of vertical structures extending from a substrate, and a bottom source/drain formed in each of the plurality of vertical structures in a saddle area, wherein the saddle area comprises a saddle trench formed through the plurality of vertical structures. The DRAM device may further include a dielectric film formed over the plurality of vertical structures in the saddle area, wherein the dielectric film is present along a portion of the plurality of bitlines and along just a first sidewall the plurality of vertical structures in the saddle area, and a fill material over the plurality of vertical structures of the saddle area, wherein the fill material directly contacts the plurality of bitlines.

Abstract: Disclosed herein are approaches for forming a uniform film with reduced surface roughness for photonic applications. One method includes providing a workpiece including a contact etch stop layer (CESL) over a device layer, patterning the CESL to expose an upper surface of the device layer in a waveguide target area, and patterning a waveguide from a dielectric film formed over the waveguide target area. The method may further include directing ions into an upper surface of the waveguide using a high-temperature ion implant to decrease a surface roughness of the upper surface of the waveguide.

Abstract: Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). In one approach, a method may include forming a plurality of bridge layers in a substrate by directing first ions into the substrate while the substrate is at a low temperature, wherein the ions are directed into the substrate in a series of implants, and annealing the plurality of bridge layers. The method may further include forming a contact by directing second ions into an upper surface of the plurality of bridge layers while the substrate is at the low temperature, and forming a pillar over the contact.

Abstract: Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

Abstract: Disclosed herein are approaches for forming a shallow trench isolation (STI) to improve extremely thin silicon on insulator (ETSOI) device performance. In one approach, a method may include providing a device stack comprising a buried oxide (BOX) layer in a substrate, patterning a hardmask over the substrate, and forming a plurality of isolation regions in the device stack, wherein the plurality of isolation regions extend through the box layer and the substrate. The method may further include forming a well mask over the device stack, wherein an opening through the well mask exposes a first isolation region of the plurality of isolation regions, and modifying a stress of a material of the first isolation region by implanting the first isolation region of the plurality of isolation regions.

Abstract: Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). One DRAM device may include plurality of pillars extending from a base layer, and a spacer layer formed along just a lower portion of each of the plurality of pillars. The DRAM further includes a body contact and a cap between the plurality of pillars, wherein the body contact is formed over the spacer layer, and a gate formed around the plurality of pillars. The DRAM further includes a bottom source/drain formed in the base layer and a top source/drain formed in each pillar of the plurality of pillars, wherein the top source/drain extends above the gate.

Abstract: Disclosed herein are approaches for forming contacts in a 4F2 vertical dynamic random-access memory device. One method includes forming a hardmask over a plurality of pillars and over a plurality of anchors, wherein the pillars are separated from one another by a STI, and removing the STI and etching through the hardmask to form a plurality of gate trenches. The method may further include delivering a capping material to the pillars at a non-zero angle relative to a perpendicular extending from an upper surface of the pillars, wherein the capping material forms a capping layer along an upper portion of the pillars without forming the capping layer along a lower portion of the pillars. The method may further include etching the pillars to trim the lower portion of the pillars, and forming a plurality of contacts in the upper portion of the pillars.

Abstract: Methods for processing a dielectric film to improve its uniformity of thickness and refractive index are disclosed. The dielectric film is deposited using conventional approaches, such as chemical vapor deposition (CVD) or spin coating. The workpiece, with the applied dielectric film is then processed to improve the uniformity of the thickness. This processing may comprise implanting a thinning species to the thicker portions of the dielectric film to reduce the thickness of these portions. The thinning species may be silicon or another suitable species. This processing may alternatively or additionally include implanting a thickening species to the thinner portions of the dielectric film to increase their thickness. The thickening species may be helium or another suitable species. This approach may reduce the variation in thickness by 50% or more.