Patents by Inventor Qintao Zhang

Qintao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194518
    Abstract: Disclosed herein are approaches for forming a shallow trench isolation (STI) to improve extremely thin silicon on insulator (ETSOI) device performance. In one approach, a method may include providing a device stack comprising a buried oxide (BOX) layer in a substrate, patterning a hardmask over the substrate, and forming a plurality of isolation regions in the device stack, wherein the plurality of isolation regions extend through the box layer and the substrate. The method may further include forming a well mask over the device stack, wherein an opening through the well mask exposes a first isolation region of the plurality of isolation regions, and modifying a stress of a material of the first isolation region by implanting the first isolation region of the plurality of isolation regions.
    Type: Application
    Filed: December 12, 2022
    Publication date: June 13, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Wei Zou
  • Publication number: 20240188279
    Abstract: Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). One DRAM device may include plurality of pillars extending from a base layer, and a spacer layer formed along just a lower portion of each of the plurality of pillars. The DRAM further includes a body contact and a cap between the plurality of pillars, wherein the body contact is formed over the spacer layer, and a gate formed around the plurality of pillars. The DRAM further includes a bottom source/drain formed in the base layer and a top source/drain formed in each pillar of the plurality of pillars, wherein the top source/drain extends above the gate.
    Type: Application
    Filed: December 5, 2022
    Publication date: June 6, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Sipeng Gu, Qintao Zhang
  • Publication number: 20240172419
    Abstract: Disclosed herein are approaches for forming contacts in a 4F2 vertical dynamic random-access memory device. One method includes forming a hardmask over a plurality of pillars and over a plurality of anchors, wherein the pillars are separated from one another by a STI, and removing the STI and etching through the hardmask to form a plurality of gate trenches. The method may further include delivering a capping material to the pillars at a non-zero angle relative to a perpendicular extending from an upper surface of the pillars, wherein the capping material forms a capping layer along an upper portion of the pillars without forming the capping layer along a lower portion of the pillars. The method may further include etching the pillars to trim the lower portion of the pillars, and forming a plurality of contacts in the upper portion of the pillars.
    Type: Application
    Filed: November 18, 2022
    Publication date: May 23, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Sipeng Gu
  • Publication number: 20240145217
    Abstract: Methods for processing a dielectric film to improve its uniformity of thickness and refractive index are disclosed. The dielectric film is deposited using conventional approaches, such as chemical vapor deposition (CVD) or spin coating. The workpiece, with the applied dielectric film is then processed to improve the uniformity of the thickness. This processing may comprise implanting a thinning species to the thicker portions of the dielectric film to reduce the thickness of these portions. The thinning species may be silicon or another suitable species. This processing may alternatively or additionally include implanting a thickening species to the thinner portions of the dielectric film to increase their thickness. The thickening species may be helium or another suitable species. This approach may reduce the variation in thickness by 50% or more.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Qintao Zhang, Eric Jay Simmons, JR., Jared Traynor, Wei Zou, Miguel Fung, Samphy Hong
  • Publication number: 20240128131
    Abstract: A camera may capture reflected light from the surface of the wafer during a semiconductor process that adds or removes material from the wafer, such as an etch process. To accurately determine an endpoint for the process, a camera sampling rate and light source intensity may be optimized in the process recipe. Optimizing the light source intensity may include characterizing light intensities that will be reflected from the waiver using an image of the wafer. Pixel intensities may be used to adjust the light source intensity to compensate for more complex wafer patterns. Optimizing the camera sampling rates may include nondestructively rotating a view of the wafer and converting the sampled intensities to the frequency domain. The camera sampling rate may be increased or decreased to remove spatial noise from the image without oversampling unnecessarily. These optimized parameters may then generate a clean, repeatable trace for endpoint determination.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Avishay Vaxman, Qintao Zhang, Jeffrey P. Koch, David P. Surdock, Wayne R. Swart, David J. Lee, Samphy Hong, Aldrin Bernard Vincent Eddy, Daniel G. Deyo
  • Publication number: 20240121937
    Abstract: Disclosed herein are approaches for forming contacts in a 4F2 vertical dynamic random-access memory device. One method includes providing a plurality of fins extending from a substrate, forming a spacer layer over the plurality of fins, and etching the substrate to expose a base portion of the plurality of fins. The method may include forming a doped layer along the base portion of the plurality of fins and along an upper surface of the substrate, and forming an oxide spacer over the doped layer.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Sipeng Gu, Qintao Zhang, Kyu-ha Shim
  • Patent number: 11955533
    Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 9, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Sipeng Gu, Baonian Guo, Qintao Zhang, Wei Zou, Kyuha Shim
  • Patent number: 11948799
    Abstract: Provided here are methods and manufacturing systems to implant protons into SiC IGBT devices at multiple depths in the drift layer of the SiC IGBT device. Provides are SiC IGBT devices manufactured with process steps including multiple proton implant processes where the SiC IGBT device is irradiated with ion to affect proton implantation into the SiC IGBT device at multiple depths in the drift region to reduced minority carrier lifetime.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: April 2, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Wei Zou
  • Patent number: 11942324
    Abstract: A method of promoting adhesion between a dielectric layer of a semiconductor device and a metal fill deposited within a trench in the dielectric layer, including performing an ion implantation process wherein an ion beam formed of an ionized dopant species is directed into the trench at an acute angle relative to a top surface of the dielectric layer to form an implantation layer in a sidewall of the trench, and depositing a metal fill in the trench atop an underlying bottom metal layer, wherein the metal fill adheres to the sidewall.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: March 26, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Jun-Feng Lu, Ting Cai, Ma Ning, Weiye He, Jian Kang
  • Publication number: 20240079236
    Abstract: Disclosed herein are approaches for forming a SiC MOSFET including at least one trench with rounded corners. In one approach, a method may include providing a masking layer over a silicon carbide (SiC) layer, wherein an opening is formed in the masking layer, and providing a sidewall spacer along a sidewall of the opening of the masking layer. The method may further include forming an implant region within the SiC layer by directing ions through the opening defined by the sidewall spacer, performing a first etch to the SiC layer, wherein the first etch forms a central recess and a set of shoulder regions adjacent the central recess, and performing a second etch to remove the set of shoulder regions.
    Type: Application
    Filed: September 2, 2022
    Publication date: March 7, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Sipeng Gu
  • Publication number: 20240072059
    Abstract: Disclosed herein are approaches for forming a FDSOI, single diffusion break device. In one approach, a method may include providing a plurality of gates in a stack of layers, wherein each gate of the plurality of gates comprises a sidewall spacer, and forming a mask over the stack of layers, wherein an opening through the mask exposes a dummy gate of the plurality of gates. The method may further comprise etching a gate material of the dummy gate to form a recess in a silicon-on-insulator (SOI) layer of the stack of layers, implanting oxygen ions into the recess, and annealing the SOI layer within the recess to form an isolation area.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Sipeng Gu, Qintao Zhang
  • Patent number: 11881405
    Abstract: Disclosed herein are approaches for reducing buried channel recess depth using a non-doping ion implant prior to formation of the buried channel. In one approach, a method may include providing an oxide layer over a substrate, performing a non-doping implantation process through the oxide layer to form an amorphous region in the substrate, and forming a photoresist over the oxide layer. The method may further include forming a buried layer in the substrate by implanting the substrate through an opening in the photoresist, and performing an oxidation and dopant drive-in process to the amorphous region and to the buried layer to form a second oxide layer.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: January 23, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Wei Zou
  • Patent number: 11882695
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: January 23, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 11875995
    Abstract: A method may include providing a substrate, where the substrate includes a first main surface and a second main surface, opposite the first main surface. The second main surface may include a stress compensation layer. The method may include directing ions to the stress compensation layer in an ion implant procedure. The ion implant procedure may include exposing a first region of the stress compensation layer to a first implant process, wherein a second region of the stress compensation layer is not exposed to the first implant process.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 16, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Scott Falk, Jun-Feng Lu, Qintao Zhang
  • Publication number: 20230369050
    Abstract: A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.
    Type: Application
    Filed: August 21, 2020
    Publication date: November 16, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Rajesh Prasad, Jun-Feng Lu
  • Patent number: 11804537
    Abstract: Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: October 31, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, Wei Zou, Hans-Joachim L. Gossmann
  • Patent number: 11798982
    Abstract: Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: October 24, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, Jason Appell, David J. Lee
  • Patent number: 11728383
    Abstract: A P-type field effect transistor (PFET) device and a method for fabricating a PFET device using fully depleted silicon on insulator (FDSOI) technology is disclosed. The method includes introducing germanium into the channel layer using ion implantation. This germanium implant increases the axial stress in the channel layer, improving device performance. This implant may be performed at low temperatures to minimize damage to the crystalline structure. Further, rather than using a long duration, high temperature anneal process, the germanium implanted in the channel layer may be annealed using a laser anneal or a rapid temperature anneal. The implanted regions are re-crystallized using the channel layer that is beneath the gate as the seed layer. In some embodiments, an additional oxide spacer is used to further separate the raised source and drain regions from the gate.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 15, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Sipeng Gu, Wei Zou, Kyu-Ha Shim, Qintao Zhang
  • Publication number: 20230253208
    Abstract: Disclosed herein are approaches for reducing buried channel recess depth using a non-doping ion implant prior to formation of the buried channel. In one approach, a method may include providing an oxide layer over a substrate, performing a non-doping implantation process through the oxide layer to form an amorphous region in the substrate, and forming a photoresist over the oxide layer. The method may further include forming a buried layer in the substrate by implanting the substrate through an opening in the photoresist, and performing an oxidation and dopant drive-in process to the amorphous region and to the buried layer to form a second oxide layer.
    Type: Application
    Filed: February 4, 2022
    Publication date: August 10, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Wei Zou
  • Patent number: 11721743
    Abstract: A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: August 8, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Wei Zou, Samphy Hong