Patents by Inventor Qintao Zhang

Qintao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250081583
    Abstract: Devices and methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong
  • Publication number: 20250038000
    Abstract: Disclosed herein are methods for forming MOSFET trenches with improved corner properties. In some embodiments, a method may include providing a device structure including an epitaxial layer and a hard mask over the epitaxial layer, and forming a trench through the well and the epitaxial layer, wherein the trench is defined by a sidewall, a bottom, and a corner at an intersection of the sidewall and the bottom. The method may further include implanting the device structure by delivering ions into the corner and into the bottom of the trench, and etching the trench to increase rounding of the corner.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Qintao ZHANG, Ludovico MEGALINI, Wei ZOU, Hans-Joachim L. GOSSMANN, William O. CHARLES
  • Patent number: 12183794
    Abstract: Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: December 31, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong
  • Publication number: 20240411085
    Abstract: Disclosed herein are approaches for adjusting local refractive index for photonics IC systems using selective waveguide ion implantation. In one approach, a method may include depositing an optical device film atop a base layer, patterning the optical device film into a plurality of sections, and implanting a first section of the plurality of sections of the optical device film to adjust a refractive index of the first section.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 12, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Qintao ZHANG, Eric Jay SIMMONS, Mayrita ARRANDALE, Judeth Campbell SOUKUP, David J. LEE, Samphy HONG
  • Publication number: 20240405079
    Abstract: Disclosed herein are approaches for creating high electron mobility transistors with reduced contact resistance. In one approach, a method of forming a semiconductor device may include applying a first patterned mask on top of layered stack, wherein the layered stack includes a substrate, a buffer layer disposed over the substrate, a channel layer disposed above the buffer layer, and a barrier layer disposed above the channel layer. The method may further include forming, through an opening of the patterned mask, a source/drain contact in the barrier layer by delivering a first implant to the layered stack, and performing an etch process to form a contact opening in the source/drain contact. The method may further include performing a second implant to the source/drain contact, wherein the second implant is directed into the contact opening.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Qintao ZHANG, Michel KHOURY
  • Patent number: 12087585
    Abstract: Disclosed herein are methods for forming a buried layer using a low-temperature ion implant. In some embodiments a method may include providing an opening through a mask, wherein the mask is formed directly atop a substrate, and forming a buried layer in the substrate by performing a low-temperature ion implant through the opening of the mask. The method may further include forming an oxide layer over the substrate including over the buried layer.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: September 10, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, Wei Zou, Judy Campbell Soukup
  • Publication number: 20240292599
    Abstract: Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). An example DRAM device may include a plurality of pillars extending from a base of a substrate, a gate formed around the plurality of pillars, and a buried bitline formed within the base, wherein an upper surface of the buried bitline is recessed below an upper surface of the base. The DRAM device may further include a bottom source/drain formed beneath the plurality of pillars, and a contact formed in the bottom source/drain, between the plurality of pillars.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 29, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Sipeng Gu, Qintao Zhang
  • Publication number: 20240268095
    Abstract: Disclosed are approaches for forming 4F2 vertical DRAM devices including buried bitlines. One DRAM device may include a plurality of bitlines between a plurality of vertical structures extending from a substrate, and a bottom source/drain formed in each of the plurality of vertical structures in a saddle area, wherein the saddle area comprises a saddle trench formed through the plurality of vertical structures. The DRAM device may further include a dielectric film formed over the plurality of vertical structures in the saddle area, wherein the dielectric film is present along a portion of the plurality of bitlines and along just a first sidewall the plurality of vertical structures in the saddle area, and a fill material over the plurality of vertical structures of the saddle area, wherein the fill material directly contacts the plurality of bitlines.
    Type: Application
    Filed: February 3, 2023
    Publication date: August 8, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Sipeng Gu
  • Publication number: 20240255700
    Abstract: Disclosed herein are approaches for forming a uniform film with reduced surface roughness for photonic applications. One method includes providing a workpiece including a contact etch stop layer (CESL) over a device layer, patterning the CESL to expose an upper surface of the device layer in a waveguide target area, and patterning a waveguide from a dielectric film formed over the waveguide target area. The method may further include directing ions into an upper surface of the waveguide using a high-temperature ion implant to decrease a surface roughness of the upper surface of the waveguide.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 1, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Eric Jay Simmons, Qintao Zhang, Wei Zou, Andrew Michael Waite, Jared Forrest Traynor, Miguel Sam Fung, Vincent V. Granuzzo, David J. Lee
  • Publication number: 20240251546
    Abstract: Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). In one approach, a method may include forming a plurality of bridge layers in a substrate by directing first ions into the substrate while the substrate is at a low temperature, wherein the ions are directed into the substrate in a series of implants, and annealing the plurality of bridge layers. The method may further include forming a contact by directing second ions into an upper surface of the plurality of bridge layers while the substrate is at the low temperature, and forming a pillar over the contact.
    Type: Application
    Filed: January 23, 2023
    Publication date: July 25, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Sipeng Gu, Qintao Zhang
  • Patent number: 12046473
    Abstract: Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: July 23, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, Vittoriano Ruscio, Wei Zou, David J. Lee
  • Publication number: 20240194518
    Abstract: Disclosed herein are approaches for forming a shallow trench isolation (STI) to improve extremely thin silicon on insulator (ETSOI) device performance. In one approach, a method may include providing a device stack comprising a buried oxide (BOX) layer in a substrate, patterning a hardmask over the substrate, and forming a plurality of isolation regions in the device stack, wherein the plurality of isolation regions extend through the box layer and the substrate. The method may further include forming a well mask over the device stack, wherein an opening through the well mask exposes a first isolation region of the plurality of isolation regions, and modifying a stress of a material of the first isolation region by implanting the first isolation region of the plurality of isolation regions.
    Type: Application
    Filed: December 12, 2022
    Publication date: June 13, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Wei Zou
  • Publication number: 20240188279
    Abstract: Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). One DRAM device may include plurality of pillars extending from a base layer, and a spacer layer formed along just a lower portion of each of the plurality of pillars. The DRAM further includes a body contact and a cap between the plurality of pillars, wherein the body contact is formed over the spacer layer, and a gate formed around the plurality of pillars. The DRAM further includes a bottom source/drain formed in the base layer and a top source/drain formed in each pillar of the plurality of pillars, wherein the top source/drain extends above the gate.
    Type: Application
    Filed: December 5, 2022
    Publication date: June 6, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Sipeng Gu, Qintao Zhang
  • Publication number: 20240172419
    Abstract: Disclosed herein are approaches for forming contacts in a 4F2 vertical dynamic random-access memory device. One method includes forming a hardmask over a plurality of pillars and over a plurality of anchors, wherein the pillars are separated from one another by a STI, and removing the STI and etching through the hardmask to form a plurality of gate trenches. The method may further include delivering a capping material to the pillars at a non-zero angle relative to a perpendicular extending from an upper surface of the pillars, wherein the capping material forms a capping layer along an upper portion of the pillars without forming the capping layer along a lower portion of the pillars. The method may further include etching the pillars to trim the lower portion of the pillars, and forming a plurality of contacts in the upper portion of the pillars.
    Type: Application
    Filed: November 18, 2022
    Publication date: May 23, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Sipeng Gu
  • Publication number: 20240145217
    Abstract: Methods for processing a dielectric film to improve its uniformity of thickness and refractive index are disclosed. The dielectric film is deposited using conventional approaches, such as chemical vapor deposition (CVD) or spin coating. The workpiece, with the applied dielectric film is then processed to improve the uniformity of the thickness. This processing may comprise implanting a thinning species to the thicker portions of the dielectric film to reduce the thickness of these portions. The thinning species may be silicon or another suitable species. This processing may alternatively or additionally include implanting a thickening species to the thinner portions of the dielectric film to increase their thickness. The thickening species may be helium or another suitable species. This approach may reduce the variation in thickness by 50% or more.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Qintao Zhang, Eric Jay Simmons, JR., Jared Traynor, Wei Zou, Miguel Fung, Samphy Hong
  • Publication number: 20240128131
    Abstract: A camera may capture reflected light from the surface of the wafer during a semiconductor process that adds or removes material from the wafer, such as an etch process. To accurately determine an endpoint for the process, a camera sampling rate and light source intensity may be optimized in the process recipe. Optimizing the light source intensity may include characterizing light intensities that will be reflected from the waiver using an image of the wafer. Pixel intensities may be used to adjust the light source intensity to compensate for more complex wafer patterns. Optimizing the camera sampling rates may include nondestructively rotating a view of the wafer and converting the sampled intensities to the frequency domain. The camera sampling rate may be increased or decreased to remove spatial noise from the image without oversampling unnecessarily. These optimized parameters may then generate a clean, repeatable trace for endpoint determination.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Avishay Vaxman, Qintao Zhang, Jeffrey P. Koch, David P. Surdock, Wayne R. Swart, David J. Lee, Samphy Hong, Aldrin Bernard Vincent Eddy, Daniel G. Deyo
  • Publication number: 20240121937
    Abstract: Disclosed herein are approaches for forming contacts in a 4F2 vertical dynamic random-access memory device. One method includes providing a plurality of fins extending from a substrate, forming a spacer layer over the plurality of fins, and etching the substrate to expose a base portion of the plurality of fins. The method may include forming a doped layer along the base portion of the plurality of fins and along an upper surface of the substrate, and forming an oxide spacer over the doped layer.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Sipeng Gu, Qintao Zhang, Kyu-ha Shim
  • Patent number: 11955533
    Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 9, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Sipeng Gu, Baonian Guo, Qintao Zhang, Wei Zou, Kyuha Shim
  • Patent number: 11948799
    Abstract: Provided here are methods and manufacturing systems to implant protons into SiC IGBT devices at multiple depths in the drift layer of the SiC IGBT device. Provides are SiC IGBT devices manufactured with process steps including multiple proton implant processes where the SiC IGBT device is irradiated with ion to affect proton implantation into the SiC IGBT device at multiple depths in the drift region to reduced minority carrier lifetime.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: April 2, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Wei Zou
  • Patent number: 11942324
    Abstract: A method of promoting adhesion between a dielectric layer of a semiconductor device and a metal fill deposited within a trench in the dielectric layer, including performing an ion implantation process wherein an ion beam formed of an ionized dopant species is directed into the trench at an acute angle relative to a top surface of the dielectric layer to form an implantation layer in a sidewall of the trench, and depositing a metal fill in the trench atop an underlying bottom metal layer, wherein the metal fill adheres to the sidewall.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: March 26, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Jun-Feng Lu, Ting Cai, Ma Ning, Weiye He, Jian Kang