Abstract: A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: A one-time programmable (OTP) vertical field-effect transistor (VFET) can be fabricated on the top surface of an integrated circuit (IC) substrate having a fin. A doped layer can be deposited onto the top surface to create an OTP VFET drain. A dielectric layer can be formed onto side surfaces of the fin, and a gate dielectric layer formed onto side surfaces of the dielectric layer. A metal layer formed onto side surfaces of the gate dielectric layer can create an OTP VFET gate. An electrically insulative top spacer layer can then be attached to top edges of the dielectric, the gate dielectric layer, and the metal layer. A doped structure formed onto the top surface of the fin can create an OTP VFET source. A voltage applied to a portion of the gate dielectric layer can cause dielectric breakdown, which can be used to store a data value.

Abstract: Methods of forming semiconductor devices include forming structures having an inner vertical layer and spacers on sidewalls of the inner vertical layer on a first region and a second region of a gate layer. The inner vertical layer is etched in only the first region to expose inner sidewalls of the spacers in the first region. The gate layer is etched using the remaining inner vertical layers and the spacers as a mask to form first gates in the first region and second gates in the second region. The first gates have a smaller gate length than a gate length of the second gates.

Abstract: An inductor device includes a substrate, and a plurality of first trenches including a first metal on the substrate to form first metal layers. The first metal layers are arranged substantially parallel to the substrate. A plurality of second trenches including a second metal is over the first metal layers and includes first portions and second portions. The first portions are substantially parallel to and interdigitate the first metal layers. The second portions are substantially perpendicular to the first portions, extend from ends of the first portions, and are oriented in opposite directions such that the second portions extend over ends of adjacent first metal layers. A plurality of vias connects the first metal layers to the second metal layers. A plurality of magnetic trenches is over the first metal layers, under the second metal layers, and substantially parallel to the second portions of the plurality of second trenches.

Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.

Abstract: An inductor device includes a substrate, and a plurality of first trenches including a first metal on the substrate to form first metal layers. The first metal layers are arranged substantially parallel to the substrate. A plurality of second trenches including a second metal is over the first metal layers and includes first portions and second portions. The first portions are substantially parallel to and interdigitate the first metal layers. The second portions are substantially perpendicular to the first portions, extend from ends of the first portions, and are oriented in opposite directions such that the second portions extend over ends of adjacent first metal layers. A plurality of vias connects the first metal layers to the second metal layers. A plurality of magnetic trenches is over the first metal layers, under the second metal layers, and substantially parallel to the second portions of the plurality of second trenches.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a nanosheet capacitor by forming a first nanosheet stack over a substrate. The first nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A second nanosheet stack is formed over the substrate adjacent to the first nanosheet stack. The second nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. Exposed portions of the first and second nanosheets of the second nanosheet stack are doped and gates are formed over channel regions of the first and second nanosheet stacks.

Abstract: A method is presented for integrating a first nanosheet transistor and a second nanosheet transistor on a chip. The method includes forming a first stack of alternating layers for the first gate dielectric nanosheet transistor and a second stack of alternating layers for the second gate dielectric nanosheet transistor, removing a first set of sacrificial layers of the first stack of alternating layers of the first gate dielectric nanosheet transistor and removing a first set of sacrificial layers of the second stack of alternating layers of the second gate dielectric nanosheet transistor, and removing a second set of sacrificial layers of the first stack of alternating layers. The method further includes annealing a second set of sacrificial layers to subsequently remove the second set of sacrificial layers of the second stack of alternating layers, and forming a first gate dielectric nanosheet transistor and a second gate dielectric nanosheet transistor.

Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.

Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.

Abstract: An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second substrate regions on opposite sides thereof. Vertical transistors are operably arranged on the doped upper surface section at the first substrate region. P-I-N diodes are operably arranged on the doped upper surface section at the second substrate region.

Abstract: A semiconductor device includes a substrate and a field effect transistor (FET) arranged on the substrate. The FET includes a gate positioned on the substrate. The gate includes a nanosheet extending through a channel region of the gate. The FET includes a pair of source/drains arranged on opposing sides of the gate. The semiconductor device further includes a bipolar junction transistor (BJT) arranged adjacent to the FET on the substrate. The BJT includes an emitter and a collector. The BJT includes a nanosheet including a semiconductor material extending from the emitter to the collector, with a doped semiconductor material arranged above and below the nanosheet.

Abstract: An inductor device includes a substrate, and a plurality of first trenches including a first metal on the substrate to form first metal layers. The first metal layers are arranged substantially parallel to the substrate. A plurality of second trenches including a second metal is over the first metal layers and includes first portions and second portions. The first portions are substantially parallel to and interdigitate the first metal layers. The second portions are substantially perpendicular to the first portions, extend from ends of the first portions, and are oriented in opposite directions such that the second portions extend over ends of adjacent first metal layers. A plurality of vias connects the first metal layers to the second metal layers. A plurality of magnetic trenches is over the first metal layers, under the second metal layers, and substantially parallel to the second portions of the plurality of second trenches.

Abstract: Nanosheet FET devices having substrate isolation layers are provided, as well as methods for fabricating nanosheet FET devices with substrate isolation layers. For example, a semiconductor device includes a nanosheet stack structure formed on a substrate, which includes a rare earth oxide (REO) layer formed on the substrate, and a semiconductor channel layer disposed adjacent to the REO layer. A metal gate structure is formed over the nanosheet stack structure, and a gate insulating spacer is disposed on sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer. Source/drain regions are formed in contact with the exposed end portions of the semiconductor channel layer. A portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the substrate.

Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure that includes a fin on a semiconductor substrate, forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin and epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin structure.

Abstract: Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

Abstract: Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

Abstract: A semiconductor device includes a substrate and a field effect transistor (FET) arranged on the substrate. The FET includes a gate positioned on the substrate. The gate includes a nanosheet extending through a channel region of the gate. The FET includes a pair of source/drains arranged on opposing sides of the gate. The semiconductor device further includes a bipolar junction transistor (BJT) arranged adjacent to the FET on the substrate. The BJT includes an emitter and a collector. The BJT includes a nanosheet including a semiconductor material extending from the emitter to the collector, with a doped semiconductor material arranged above and below the nanosheet.

Abstract: Methods of forming semiconductor devices include forming structures having an inner vertical layer and spacers on sidewalls of the inner vertical layer on a first region and a second region of a gate layer. The inner vertical layer is etched in only the first region to expose inner sidewalls of the spacers in the first region. The gate layer is etched using the remaining inner vertical layers and the spacers as a mask to form first gates in the first region and second gates in the second region. The first gates have a smaller gate length than a gate length of the second gates.