Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: A method may include providing a substrate, where the substrate includes a first main surface and a second main surface, opposite the first main surface. The second main surface may include a stress compensation layer. The method may include directing ions to the stress compensation layer in an ion implant procedure. The ion implant procedure may include exposing a first region of the stress compensation layer to a first implant process, wherein a second region of the stress compensation layer is not exposed to the first implant process.

Abstract: Embodiments are directed to devices and methods for integrating laterally diffused metal oxide semiconductor (LDMOS) technology on vertical field effect transistor (VFET) technology, which enables VFET applications to be broadened to include power amplifiers. By providing a combined asymmetric underlapped drain, high current, low subthreshold slope and LDMOS lightly doped drain, high drain resistance and high drain voltage are enabled.

Abstract: The present disclosure relates to a programmable device. The programmable device comprises a first vertical transistor; and a second vertical transistor coupled to the first vertical transistor via a shared terminal, wherein: a first gate dielectric of the first vertical transistor has a first thickness and a second gate dielectric of the second vertical transistor has a second thickness, the first thickness being greater than the second thickness, and the second gate dielectric breaks down based on an application of a gate voltage that is lower than a first breakdown voltage of the first gate dielectric and higher than a second breakdown voltage of the second gate dielectric.

Abstract: A method of making an inductor device includes forming a first metal layer and an ILD on a substrate, patterning a trench perpendicular to the first metal layer in the ILD, and depositing a magnetic material. The method includes depositing another ILD and patterning a via adjacent to the trench that extends from the first metal layer to a surface of the ILD. The method includes patterning trenches in the ILD, with a first portion over and adjacent to and parallel to the first metal layer, and a second portion perpendicular to the first portion and extending from an end of the first portion to the via. The first metal layer and trenches are connected to through the via. The method includes depositing a metal in the via, and depositing a metal in the trenches to form a second metal layer connected to the first metal layer through the via.

Abstract: Provided herein are approaches for forming a gate dielectric layer for a DRAM device, the method including providing a substrate having a recess formed therein, the recess including a sidewall surface and a bottom surface. The method may further include performing an ion implant into just the bottom surface of the recess, and forming a gate dielectric layer along the bottom surface of the recess and along the sidewall surface of the recess. Once formed, a thickness of the gate dielectric layer along the sidewall surface is approximately the same as a thickness of the gate dielectric layer along the bottom surface of the recess. In some embodiments, the gate dielectric layer is thermally grown within the recess. In some embodiments, the ion implant is performed after a mask layer atop the substrate is removed.

Abstract: Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and defining field-effect transistor (FET) and diode regions. The method further includes depositing a mask, where the mask covers only the FET region while leaving the diode region uncovered. The method further includes doping the material in the diode region with a dopant, implanting epitaxial material with another dopant to form PN junctions, stripping the mask from the structure, forming a metal gate conductor over the FET region, and depositing a metal over the substrate to create terminals.

Abstract: Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

Abstract: Provided herein are approaches for forming a gate dielectric layer for a DRAM device, the method including providing a substrate having a recess formed therein, the recess including a sidewall surface and a bottom surface. The method may further include performing an ion implant into just the bottom surface of the recess, and forming a gate dielectric layer along the bottom surface of the recess and along the sidewall surface of the recess. Once formed, a thickness of the gate dielectric layer along the sidewall surface is approximately the same as a thickness of the gate dielectric layer along the bottom surface of the recess. In some embodiments, the gate dielectric layer is thermally grown within the recess. In some embodiments, the ion implant is performed after a mask layer atop the substrate is removed.

Abstract: The present disclosure relates to a programmable device. The programmable device comprises a first vertical transistor; and a second vertical transistor coupled to the first vertical transistor via a shared terminal, wherein: a first gate dielectric of the first vertical transistor has a first thickness and a second gate dielectric of the second vertical transistor has a second thickness, the first thickness being greater than the second thickness, and the second gate dielectric breaks down based on an application of a gate voltage that is lower than a first breakdown voltage of the first gate dielectric and higher than a second breakdown voltage of the second gate dielectric.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: A semiconductor device includes a substrate and a field effect transistor (FET) arranged on the substrate. The FET includes a gate positioned on the substrate. The gate includes a nanosheet extending through a channel region of the gate. The FET includes a pair of source/drains arranged on opposing sides of the gate. The semiconductor device further includes a bipolar junction transistor (BJT) arranged adjacent to the FET on the substrate. The BJT includes an emitter and a collector. The BJT includes a nanosheet including a semiconductor material extending from the emitter to the collector, with a doped semiconductor material arranged above and below the nanosheet.

Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.

Abstract: Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

Abstract: Nanosheet FET devices having substrate isolation layers are provided, as well as methods for fabricating nanosheet FET devices with substrate isolation layers. For example, a semiconductor device includes a nanosheet stack structure formed on a substrate, which includes a rare earth oxide (REO) layer formed on the substrate, and a semiconductor channel layer disposed adjacent to the REO layer. A metal gate structure is formed over the nanosheet stack structure, and a gate insulating spacer is disposed on sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer. Source/drain regions are formed in contact with the exposed end portions of the semiconductor channel layer. A portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the substrate.

Abstract: Embodiments of the invention are directed to fabrication operations for co-integrating standard-gate (SG) and extended-gate (EG) nanosheet/nanowire transistors on the same substrate. The SG and EG nanosheet/nanowire transistors share certain fabrication operations for certain features. For example, the processes to form the bottommost channel nanosheet, the bottommost sacrificial nanosheet, and the topmost channel nanosheet are the same for SG nanosheet transistors and the EG nanosheet transistors. Because the thickness of the sacrificial nanosheet needs to be thicker for EG nanosheet transistors, a thickness of the bottommost sacrificial nanosheet is selected to accommodate the design parameters of the EG nanosheet transistor. Because the thickness of the SG and the EG channel nanosheets do not need to be different, a thickness of the bottommost channel nanosheet and the topmost channel nanosheet can be selected to accommodate the design parameters of both the SG and the EG nanosheet transistors.

Abstract: A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.

Abstract: A semiconductor device includes a buried epitaxially grown substrate and a silicon on insulator (SOI) layer. The device also includes a buried oxide (BOX) layer between the buried epitaxially grown substrate and the SOI layer, an isolation trench having first width (w1), a contact trench having a second width (w2) and a capacitive trench having a third width (w3). Methods are described that allow the formation of the trenches in a normal process flow.

Abstract: A one-time programmable (OTP) vertical field-effect transistor (VFET) can be fabricated on the top surface of an integrated circuit (IC) substrate having a fin. A doped layer can be deposited onto the top surface to create an OTP VFET drain. A dielectric layer can be formed onto side surfaces of the fin, and a gate dielectric layer formed onto side surfaces of the dielectric layer. A metal layer formed onto side surfaces of the gate dielectric layer can create an OTP VFET gate. An electrically insulative top spacer layer can then be attached to top edges of the dielectric, the gate dielectric layer, and the metal layer. A doped structure formed onto the top surface of the fin can create an OTP VFET source. A voltage applied to a portion of the gate dielectric layer can cause dielectric breakdown, which can be used to store a data value.