Abstract: Disclosed herein are methods for increasing MOSFET threshold voltage to enable higher SiC mobility. In some embodiments, a method includes providing a device structure including a dielectric layer over an epitaxial layer, patterning a hardmask layer over the dielectric layer, performing a first ion implant to form a well in the epitaxial layer, and performing a second ion implant to form an interface layer between the well and the dielectric layer.

Abstract: Provided here are methods and manufacturing systems to implant protons into SiC IGBT devices at multiple depths in the drift layer of the SiC IGBT device. Provides are SiC IGBT devices manufactured with process steps including multiple proton implant processes where the SiC IGBT device is irradiated with ion to affect proton implantation into the SiC IGBT device at multiple depths in the drift region to reduced minority carrier lifetime.

Abstract: A method of forming a metal oxide semiconductor field effect transistor with improved gate-induced drain leakage performance, the method including providing a semiconductor substrate having a gate trench formed therein, performing an ion implantation process on upper portions of sidewalls of the gate trench to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls, and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls.

Abstract: Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.

Abstract: Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

Abstract: Disclosed herein are methods for forming a buried layer using a low-temperature ion implant. In some embodiments a method may include providing an opening through a mask, wherein the mask is formed directly atop a substrate, and forming a buried layer in the substrate by performing a low-temperature ion implant through the opening of the mask. The method may further include forming an oxide layer over the substrate including over the buried layer.

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming a gate spacer layer over the device structure, and removing the gate spacer layer from a top surface of the device structure and from a first section of each of the plurality of trenches, wherein a portion of the gate spacer layer remains along a second section of each of the plurality of trenches. The method may further include forming a gate oxide layer along the first section of each of the plurality of trenches and along the portion of the gate spacer layer.

Abstract: Disclosed herein are methods for backside wafer dopant activation using a high-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a high-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

Abstract: A method for performing an ion implantation process including providing a hardmask layer disposed atop a substrate, providing a photoresist layer disposed atop the hardmask layer and defining a pattern exposing a portion of the hardmask layer, performing a room temperature ion implantation process wherein an ion beam formed of an ionized first dopant species is directed onto the exposed portion of the hardmask layer to make the exposed portion more susceptible to ion etching or wet etching, performing an etching process wherein the exposed portion of the hardmask layer is etched away to expose an underlying portion of the substrate, and performing a high energy, hot ion implantation process wherein an ion beam formed of a ionized second dopant species is directed onto the exposed portion of the substrate.

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming an oxide layer over the device structure including within each of the plurality of trenches and over a top surface of the device structure, and implanting a first portion of the oxide layer using an ion implant delivered to the device structure at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the device structure. The method may further include removing the oxide layer from the top surface of the device structure and from a sidewall of each of the plurality of trenches, wherein a second portion of the oxide layer remains along a bottom of each of the plurality of trenches.

Abstract: A method of forming a metal oxide semiconductor field effect transistor with improved gate-induced drain leakage performance, the method including providing a semiconductor substrate having a gate trench formed therein, performing an ion implantation process on upper portions of sidewalls of the gate trench to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls, and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls.

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

Abstract: Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.

Abstract: Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.

Abstract: Embodiments herein are directed to methods and devices having a stress memorization layer along a side of a substrate. In some embodiments, a method may include providing a substrate having a first main side opposite a second main side, implanting the second main side of the substrate to form an amorphous implant area, forming a stress liner over the second main side of the substrate, and annealing the stress liner to form a stress memorization layer in the amorphous implant area.

Abstract: Disclosed herein are methods for forming split-gate MOSFETs including a gate shield. In some embodiments, a method may include providing a device structure including a well formed in an epitaxial layer, forming a set of trenches through the well and the epitaxial layer, implanting the device structure to form a gate shield layer at a bottom of each of the set of trenches, and forming a gate spacer layer over the device structure including within the set of trenches.

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming an oxide layer over the device structure including within each of the plurality of trenches and over a top surface of the device structure, and implanting a first portion of the oxide layer using an ion implant delivered to the device structure at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the device structure. The method may further include removing the oxide layer from the top surface of the device structure and from a sidewall of each of the plurality of trenches, wherein a second portion of the oxide layer remains along a bottom of each of the plurality of trenches.

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

Abstract: Disclosed herein are methods for reducing MOSFET trench sidewall surface roughness. In some embodiments, a method includes providing a device structure including a well formed in an epitaxial layer, forming a plurality of trenches through the well and the epitaxial layer, and implanting the device structure to form a treated layer along a sidewall of just an upper portion of the device structure within each of the plurality of trenches. The method may further include etching the device structure to remove the treated layer.

Abstract: A method of forming a gate of a planar metal oxide semiconductor field effect transistor (MOSFET) reduces gate-drain capacitance. The method may include forming a first gate dielectric portion of the planar MOSFET with a first thickness that is configured to reduce the gate-drain capacitance of the planar MOSFET, forming a second gate dielectric portion of the planar MOSFET on the substrate with a second thickness less than the first thickness, and forming the gate of the planar MOSFET on the first gate dielectric portion and the second gate dielectric portion on the substrate.