Abstract: A dual-loop digital delay locked loop (DLL) is provided. The DLL includes a coarse loop to produce a first delayed signal and provides a wide frequency lock range. The DLL further includes a fine loop connected to the coarse loop to produce a second delayed signal and provides a tight locking. This dual-loop architecture can provide robust operation and tight synchronization over a wide range of delay variations.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: An MRAM memory integrated circuit is disclosed. Resistance, and hence logic state, is determined by discharging a first charged capacitor through an unknown cell resistive element to be sensed at a fixed voltage, and a pair of reference capacitors. The rate at which the parallel combination of capacitors discharge is between the discharge rate associated with a binary ‘1’ and ‘0’ value, and thus offers a reference for comparison.

Abstract: A method and system sense the logic state of an unknown initial data bit stored in a selected resistive memory cell. According to one method, a first count representing the logic state of the unknown initial data bit stored in the selected memory cell is generated. A second count is then generated, and represents a data bit having a first known logic state stored in the selected memory cell. A third count is then generated, and represents a data bit having a second known logic state stored in the selected memory cell. The logic state of the initial unknown data bit stored in the selected memory cell is then determined from the first, second, and third counts.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: A method and apparatus for sensing a resistive state of a resistive memory element includes producing a first current related to a resistance of a memory cell. The first current is added to a second current during a first sensing time and subtracted from a third current during a second sensing time. The first, second and third currents are integrated over time using a capacitor, and a resulting voltage signal on the capacitor is timed using a clocked counter. A time average value of a digital output of the clocked counter is then related to the resistance of the memory cell, and hence to the resistive state of the resistive memory element.

Abstract: An MRAM array includes a plurality of memory cells arranged in rows and columns are programmed, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line. According to one aspect of the present invention, a method for writing data to selected memory cells includes applying a row current to a selected word line and applying a first column current to a selected bit line. The column current is applied in a first direction. Second column currents are applied to at least the unselected bit lines adjacent the selected bit line. The second column currents are applied in a second direction that is opposite the first direction.

Abstract: The input buffer circuit includes an input stage providing a switching point voltage based on a predetermined switching point set between a first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input buffer circuit further includes an output stage. The output stage is coupled to the input stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.

Abstract: One embodiment of a complimentary input buffer uses six symmetrically arranged inverters. A pair of inverters are coupled between a respective input terminal and a respective output terminal with the input of the inverters coupled to the input terminals and the output of the inverter coupled to the output terminals. The input and output of an inverter are also coupled to each of the output terminals. Finally, a pair of inverters are connected in parallel with each other in opposite directions between the output terminals. In another embodiment, a pair of inverters are also coupled between a respective input terminal and a respective output terminal. However, the output of a respective inverter is coupled to each output terminal, and the inputs of the inverters are coupled to a voltage divider circuit connected between the output terminals.

Abstract: A method and system sense the logic state of an unknown initial data bit stored in a selected resistive memory cell. According to one method, a first count representing the logic state of the unknown initial data bit stored in the selected memory cell is generated. A second count is then generated, and represents a data bit having a first known logic state stored in the selected memory cell. A third count is then generated, and represents a data bit having a second known logic state stored in the selected memory cell. The logic state of the initial unknown data bit stored in the selected memory cell is then determined from the first, second, and third counts.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: An MRAM array includes a plurality of memory cells arranged in rows and columns are programmed, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line. According to one aspect of the present invention, a method for writing data to selected memory cells includes applying a row current to a selected word line and applying a first column current to a selected bit line. The column current is applied in a first direction. Second column currents are applied to at least the unselected bit lines adjacent the selected bit line. The second column currents are applied in a second direction that is opposite the first direction.

Abstract: A method for sensing the resistance value of a resistor-based memory cell. A current is driven through all unused row lines of a memory array while grounding the row line associated with the selected cell, thereby forcing the current through a comparatively low equivalent resistance formed by the parallel coupling of all unselected memory cells and also through a comparatively high resistance of the selected memory cell. The voltage on a column line corresponding to the selected memory cell is then measured to ground. The voltage level corresponds to either one of two resistance values (i.e., signifying either a logic “HIGH” or a logic “LOW”).

Abstract: The input buffer circuit includes an input stage providing a switching point voltage based on a predetermined switching point set between a first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input buffer circuit further includes an output stage. The output stage is coupled to the input stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.

Abstract: An MRAM memory integrated circuit is disclosed. Resistance, and hence logic state, is determined by discharging a first charged capacitor through an unknown cell resistive element to be sensed at a fixed voltage, and a pair of reference capacitors. The rate at which the parallel combination of capacitors discharge is between the discharge rate associated with a binary ‘1’ and ‘0’ value, and thus offers a reference for comparison.

Abstract: One embodiment of a complimentary input buffer uses six symmetrically arranged inverters. A pair of inverters are coupled between a respective input terminal and a respective output terminal with the input of the inverters coupled to the input terminals and the output of the inverter coupled to the output terminals. The input and output of an inverter are also coupled to each of the output terminals. Finally, a pair of inverters are connected in parallel with each other in opposite directions between the output terminals. In another embodiment, a pair of inverters are also coupled between a respective input terminal and a respective output terminal. However, the output of a respective inverter is coupled to each output terminal, and the inputs of the inverters are coupled to a voltage divider circuit connected between the output terminals.

Abstract: A method for sensing the resistance value of a resistor-based memory cell. A current is driven through all unused row lines of a memory array while grounding the row line associated with the selected cell, thereby forcing the current through a comparatively low equivalent resistance formed by the parallel coupling of all unselected memory cells and also through a comparatively high resistance of the selected memory cell. The voltage on a column line corresponding to the selected memory cell is then measured to ground. The voltage level corresponds to either one of two resistance values (i.e., signifying either a logic “HIGH” or a logic “LOW”).

Abstract: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.

Abstract: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.