Patents by Inventor R. Post

R. Post has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7895092
    Abstract: Disclosed is an integrated global shipment system that provides end-to-end visibility of the movement of a package. The integrated global shipment system employs a shipment consolidating application for integrating one or more freight tracking systems with one or more end-delivery systems. As a result, shippers are provided with complete visibility of the movement of their shipments of goods from an origin country to a destination country and till the final consignees. In addition, the integrated shipment system significantly decreases the cost of managing inventories by providing a virtual inventory solution. Under this virtual inventory solution, suppliers are able to bypass distribution centers and delay allocation of goods until after the importation of goods into a destination country.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: February 22, 2011
    Assignee: United Parcel Service of America, Inc.
    Inventors: Alan Amling, George R. Post, David S. Zamsky, Kenneth T. Rankin, Stuart D. Marcus, Bruce L. Woods
  • Publication number: 20110022534
    Abstract: Disclosed is an integrated global shipment system that provides end-to-end visibility of the movement of a package. The integrated global shipment system employs a shipment consolidating application for integrating one or more freight tracking systems with one or more end-delivery systems. As a result, shippers are provided with complete visibility of the movement of their shipments of goods from an origin country to a destination country and till the final consignees. In addition, the integrated shipment system significantly decreases the cost of managing inventories by providing a virtual inventory solution. Under this virtual inventory solution, suppliers are able to bypass distribution centers and delay allocation of goods until after the importation of goods into a destination country.
    Type: Application
    Filed: September 30, 2010
    Publication date: January 27, 2011
    Inventors: Alan Amling, George R. Post, David S. Zamsky, Kenneth T. Rankin, Stuart D. Marcus, Bruce L. Woods
  • Patent number: 7853536
    Abstract: Disclosed is an integrated global shipment system that provides end-to-end visibility of the movement of a package. The integrated global shipment system employs a shipment consolidating application for integrating one or more freight tracking systems with one or more end-delivery systems. As a result, shippers are provided with complete visibility of the movement of their shipments of goods from an origin country to a destination country and till the final consignees. In addition, the integrated shipment system significantly decreases the cost of managing inventories by providing a virtual inventory solution. Under this virtual inventory solution, suppliers are able to bypass distribution centers and delay allocation of goods until after the importation of goods into a destination country.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: December 14, 2010
    Assignee: United Parcel Service of America, Inc.
    Inventors: Alan Amling, George R. Post, David S. Zamsky, Kenneth T. Rankin, Stuart D. Marcus, Bruce L. Woods
  • Publication number: 20100257114
    Abstract: Disclosed is an integrated global shipment system that provides end-to-end visibility of the movement of a package. The integrated global shipment system employs a shipment consolidating application for integrating one or more freight tracking systems with one or more end-delivery systems. As a result, shippers are provided with complete visibility of the movement of their shipments of goods from an origin country to a destination country and till the final consignees. In addition, the integrated shipment system significantly decreases the cost of managing inventories by providing a virtual inventory solution. Under this virtual inventory solution, suppliers are able to bypass distribution centers and delay allocation of goods until after the importation of goods into a destination country.
    Type: Application
    Filed: June 16, 2010
    Publication date: October 7, 2010
    Inventors: Alan Amling, George R. Post, David S. Zamsky, Kenneth T. Rankin, Stuart D. Marcus, Bruce L. Woods
  • Patent number: 7761348
    Abstract: Disclosed is an integrated global shipment system that provides end-to-end visibility of the movement of a package. The integrated global shipment system employs a shipment consolidating application for integrating one or more freight tracking systems with one or more end-delivery systems. As a result, shippers are provided with complete visibility of the movement of their shipments of goods from an origin country to a destination country and till the final consignees. In addition, the integrated shipment system significantly decreases the cost of managing inventories by providing a virtual inventory solution. Under this virtual inventory solution, suppliers are able to bypass distribution centers and delay allocation of goods until after the importation of goods into a destination country.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: July 20, 2010
    Assignee: United Parcel Service of America, Inc.
    Inventors: Alan Amling, George R. Post, David S. Zamsky, Kenneth T. Rankin, Stuart D. Marcus, Bruce L. Woods
  • Publication number: 20090281857
    Abstract: Disclosed is an integrated global shipment system that provides end-to-end visibility of the movement of a package. The integrated global shipment system employs a shipment consolidating application for integrating one or more freight tracking systems with one or more end-delivery systems. As a result, shippers are provided with complete visibility of the movement of their shipments of goods from an origin country to a destination country and till the final consignees. In addition, the integrated shipment system significantly decreases the cost of managing inventories by providing a virtual inventory solution. Under this virtual inventory solution, suppliers are able to bypass distribution centers and delay allocation of goods until after the importation of goods into a destination country.
    Type: Application
    Filed: July 21, 2009
    Publication date: November 12, 2009
    Inventors: Alan Amling, George R. Post, David S. Zamsky, Kenneth T. Rankin, Stuart D. Marcus, Bruce L. Woods
  • Publication number: 20090242998
    Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
  • Publication number: 20090189193
    Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
    Type: Application
    Filed: April 6, 2009
    Publication date: July 30, 2009
    Applicant: INTEL CORPORATION
    Inventors: GIUSEPPE CURELLO, Ian R. Post, Chia-Hong Jan, Mark Bohr
  • Patent number: 7560780
    Abstract: A semiconductor device and method for its fabrication are described. An active region spacer may be formed on a top surface of an isolation region and adjacent to a sidewall of an active region. In one embodiment, the active region spacer may suppress the formation of metal pipes in the active region.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: July 14, 2009
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Sunit Tyagi, Mark Bohr
  • Patent number: 7541239
    Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 2, 2009
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
  • Publication number: 20080003746
    Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Giuseppe Curello, Ian R. Post, Chai-Hong Jan, Mark Bohr
  • Patent number: 7235236
    Abstract: The present invention relates to polynucleotides encoding human adenylylcyclase VI and uses thereof for enhancing cardiac function. The present invention can thus be used in the treatment of heart disease, especially congestive heart failure.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: June 26, 2007
    Assignee: The Regents of the University of California
    Inventors: H. Kirk Hammond, Paul A. Insel, Peipei Ping, Steven R. Post, Meihua Gao
  • Patent number: 7226843
    Abstract: A method including forming a transistor device having a channel region; implanting a first halo into the channel region; and implanting a second different halo into the channel region. An apparatus including a gate electrode formed on a substrate; a channel region formed in the substrate below the gate electrode and between contact points; a first halo implant comprising a first species in the channel region; and a second halo implant including a different second species in the channel region.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: June 5, 2007
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Gerhard Schrom, Ian R. Post, Mark A. Stettler
  • Publication number: 20060016812
    Abstract: The present invention is directed to a spacer for supporting stacked drawers. The spacer includes a U-shaped body portion and a post extending therefrom. The body portion defines an elongated slot for receiving a rail of the lowermost drawer. The post supports the uppermost drawer. The spacer may further include a generally vertical wall portion.
    Type: Application
    Filed: November 30, 2004
    Publication date: January 26, 2006
    Inventors: Hsi-Ming Cheng, R. Post
  • Patent number: 6979609
    Abstract: A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: December 27, 2005
    Assignee: Intel Corporation
    Inventors: Ian R. Post, Kaizad Mistry
  • Publication number: 20050077299
    Abstract: The present invention is directed to a method of forming a container comprising forming a basket portion of metal mesh material and a rail connected to the basket portion. The rail extends substantially outwardly from the outer surface of the basket portion and the rail extends continuously around the outer surface of the basket portion. In one example, the method includes forming the rail so that it does not contain or surround a free edge of the basket portion. In another example, the method includes forming the rail so that it includes an opening for containing or surrounding a free edge of the basket portion. The method may also include forming a lower rail. The present invention is also directed to a container formed by such method.
    Type: Application
    Filed: November 30, 2004
    Publication date: April 14, 2005
    Inventors: Hsi-Ming Cheng, R. Post, Christopher Hardy
  • Patent number: 6803285
    Abstract: A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: October 12, 2004
    Assignee: Intel Corporation
    Inventors: Kaizad R. Mistry, Ian R. Post
  • Patent number: 6752987
    Abstract: The present invention relates to methods and compositions for enhancing cardiac function in mammalian hearts by inserting transgenes that increase beta-adrenergic responsiveness within the myocardium. The present invention can thus be used in the treatment of heart disease, especially congestive heart failure.
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: June 22, 2004
    Assignee: The Regents of the University of California
    Inventors: H. Kirk Hammond, Paul A. Insel, Peipei Ping, Steven R. Post, Meihua Gao
  • Patent number: 6717221
    Abstract: An apparatus including a MOSFET circuit having dual threshold voltage NMOS and PMOS transistors wherein the threshold voltage of a low threshold NMOS transistor is set with a first halo implant, a threshold voltage of a high threshold voltage PMOS transistor is set with a second halo implant, and, a threshold voltage of a high threshold voltage NMOS transistor is enhanced while, a threshold voltage of a low threshold voltage PMOS transistor is compensated with a third halo implant.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: April 6, 2004
    Assignee: Intel Corporation
    Inventors: Ian R. Post, Kaizad Mistry
  • Publication number: 20040061187
    Abstract: A method including forming a transistor device having a channel region; implanting a first halo into the channel region; and implanting a second different halo into the channel region. An apparatus including a gate electrode formed on a substrate; a channel region formed in the substrate below the gate electrode and between contact points; a first halo implant comprising a first species in the channel region; and a second halo implant including a different second species in the channel region.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 1, 2004
    Inventors: Cory E. Weber, Gerhard Schrom, Ian R. Post, Mark A. Stettler