Patents by Inventor R. Post

R. Post has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6693331
    Abstract: A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: February 17, 2004
    Assignee: Intel Corporation
    Inventors: Kaizad R. Mistry, Ian R. Post
  • Publication number: 20030203579
    Abstract: A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.
    Type: Application
    Filed: April 30, 2003
    Publication date: October 30, 2003
    Inventors: Ian R. Post, Kaizad Mistry
  • Publication number: 20030190779
    Abstract: An apparatus including a MOSFET circuit having duel threshold voltage NMOS and PMOS transistors wherein the threshold voltage of a low threshold NMOS transistor is set with a first halo implant, a threshold voltage of a high threshold voltage PMOS transistor is set with a second halo implant, and, a threshold voltage of a high threshold voltage NMOS transistor is enhanced while, a threshold voltage of a low threshold voltage PMOS transistor is compensated with a third halo implant.
    Type: Application
    Filed: April 30, 2003
    Publication date: October 9, 2003
    Inventors: Ian R. Post, Kaizad Mistry
  • Patent number: 6627506
    Abstract: The present invention relates to a method of forming an isolation trench that comprises forming a recess in a substrate and forming a film upon the sidewall under conditions that cause the film to have a tensile load. The method includes filling the recess with a material that imparts a compressive load upon the film under conditions that oppose the tensile load. The present invention is particularly well suited for shallow isolation trench filling in the 0.13 micron geometry range, and smaller.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: September 30, 2003
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Ian R. Post
  • Publication number: 20030122198
    Abstract: A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.
    Type: Application
    Filed: January 2, 2002
    Publication date: July 3, 2003
    Inventors: Ian R. Post, Kaizad Mistry
  • Patent number: 6586294
    Abstract: A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: July 1, 2003
    Assignee: Intel Corporation
    Inventors: Ian R. Post, Kaizad Mistry
  • Publication number: 20030119248
    Abstract: A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.
    Type: Application
    Filed: December 4, 2002
    Publication date: June 26, 2003
    Applicant: Intel Corporation
    Inventors: Kaizad R. Mistry, Ian R. Post
  • Publication number: 20030094659
    Abstract: A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.
    Type: Application
    Filed: November 18, 1999
    Publication date: May 22, 2003
    Inventors: KAIZAD R. MISTRY, IAN R. POST
  • Publication number: 20030064414
    Abstract: The present invention is directed to methods to rapidly assess the overall coagulant properties of a patient's blood sample by inhibiting the activation of the intrinsic contact activation pathway of coagulation and activating the extrinsic pathway of coagulation. When the sample is whole blood, the resulting clotting time represents the overall coagulant activity of the plasma and cellular components of the blood, which is indicative of existing or impending pathology arising from abnormal coagulability. The invention also provides a method for measuring the risk of a patient for a thrombotic event and for monitoring the effectiveness of procoagulant/anticoagulant therapy. A blood collection apparatus suitable for use in for performing the methods of the invention is also provided.
    Type: Application
    Filed: March 28, 2002
    Publication date: April 3, 2003
    Inventors: Michael J. Benecky, Keith A. Moskowitz, Diane R. Post
  • Publication number: 20020103147
    Abstract: The present invention relates to methods and compositions for enhancing cardiac function in mammalian hearts by inserting transgenes that increase beta-adrenergic responsiveness within the myocardium. The present invention can thus be used in the treatment of heart disease, especially congestive heart failure.
    Type: Application
    Filed: December 26, 2000
    Publication date: August 1, 2002
    Inventors: H. Kirk Hammond, Paul A. Insel, Peipei Ping, Steven R. Post, Meihua Gao
  • Publication number: 20020045325
    Abstract: The present invention relates to a method of forming an isolation trench that comprises forming a recess in a substrate and forming a film upon the sidewall under conditions that cause the film to have a tensile load. The method includes filling the recess with a material that imparts a compressive load upon the film under conditions that oppose the tensile load. The present invention is particularly well suited for shallow isolation trench filling in the 0.13 micron geometry range, and smaller.
    Type: Application
    Filed: July 18, 2001
    Publication date: April 18, 2002
    Applicant: Intel Corporation
    Inventors: Kelin J. Kuhn, Ian R. Post
  • Patent number: 6368931
    Abstract: The present invention relates to a method of forming an isolation trench that comprises forming a recess in a substrate and forming a film upon the sidewall under conditions that cause the film to have a tensile load. The method includes filling the recess with a material that imparts a compressive load upon the film under conditions that oppose the tensile load. The present invention is particularly well suited for shallow isolation trench filling in the 0.13 micron geometry range, and smaller.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: April 9, 2002
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Ian R. Post
  • Patent number: 6306830
    Abstract: The present invention relates to methods and compositions for enhancing cardiac function in mammalian hearts by inserting transgenes that increase &bgr;-adrenergic responsiveness within the myocardium. The present invention can thus be used in the treatment of heart disease, especially congestive heart failure.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: October 23, 2001
    Assignee: The Regents of the University of California
    Inventors: H. Kirk Hammond, Paul A. Insel, Peipei Ping, Steven R. Post, Meihua Gao
  • Patent number: 6196143
    Abstract: The present invention is an apparatus for use as a grate clip on a traveling stoker grate assembly in a furnace or incinerator. The grate clip apparatus includes a sloping profile along a significant portion of its underside so as to prevent the build-up of ash, fuel and metallic deposits on the grate clip as it traverses a return loop.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: March 6, 2001
    Assignee: Powerhouse Technology, Inc.
    Inventor: Joseph R. Post
  • Patent number: 5887591
    Abstract: The present invention is a restraint and method for stretching the plantar fascia. A foot plate in combination with a lifting member serves to elevate the phalanges and to reduce contracture of the MTP joints. Employing a leg support shell, side railings, and straps, the present invention is able to be worn at night unobstrusively but fixedly upon the lower limb. Padding throughout the present invention ensures comfort. The user can vary the angle of dorsiflexion of the phalanges by removing and attaching various lifting members to the foot plate.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: March 30, 1999
    Inventors: Mark W. Powell, William R. Post
  • Patent number: 5722193
    Abstract: A firing mechanism having an action housing whose rotation simultaneously cocks the weapon and engages the safety. The rotation also provides access to a nipple that supports a percussion cap ignitor that is positioned underneath the weapon so that the exhaust gases are propelled downwardly and the ignitor cap is protected from the weather. The trigger pull force and distance can be individually adjusted to the preferences of the firer.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: March 3, 1998
    Inventor: Thomas R. Post
  • Patent number: 5551356
    Abstract: The present invention generally relates to a two piece grate clip with first and second grate pieces releasably secured to one another and loosely mounted on a grate bar support. The first piece and the second piece have corresponding transverse notches which form a T-shaped transverse notch when the clip is assembled. The T-shaped transverse notch allows the grate clip to be mounted onto a grate bar support. A fastener, while releasably securing the two pieces together, allows the two pieces to be extended apart and easily mounted on and removed from the grate bar support. The grate clips, when mounted and arranged side by side in rows upon each grate support bar, comprise a traveling grate stoker having a uniform, level grate surface.
    Type: Grant
    Filed: October 11, 1995
    Date of Patent: September 3, 1996
    Assignee: Powerhouse Technology, Inc.
    Inventor: Joseph R. Post
  • Patent number: 5458095
    Abstract: An electrolysis cell for use in connection with a combustion engine, for generating hydrogen and oxygen gases which are added to the fuel delivery system as a supplement to the gasoline or other hydrocarbons burned therein. The hydrogen and oxygen gases are drawn out of the cell using an electric pump or other reliable source. The outlet side of the pump is connected to the air intake manifold using a hose having a terminating insert. The insert, typically formed from copper tube bent at an appropriate angle, insures that the hydrogen and oxygen gas outlet from the pump is in the same direction as the downstream airflow in the air intake manifold.
    Type: Grant
    Filed: September 15, 1993
    Date of Patent: October 17, 1995
    Assignee: Energy Reductions Systems, Inc.
    Inventors: Donald R. Post, Douglas C. Littlefield
  • Patent number: 4967520
    Abstract: A palletized pre-cut modular small building that requires no wood cutting to assemble is constructed from four foot wide modules of plywood sheets no larger than 4.times.8 feet and 2.times.4's for the joists, studs, floor plates, headers and rafters. The design of the modules is such that they can be stacked to give a sturdy 4.times.8 foot pallet. The modules include besides floor and wall modules, door and window modules. Small components including pre-cut rafters, truss points and trim are shipped in the pallet between the upturned joists of the bottom most floor panel of the pallet.
    Type: Grant
    Filed: July 14, 1989
    Date of Patent: November 6, 1990
    Assignee: Mark R. Post
    Inventors: Russell H. Post, Jr., Mark R. Post
  • Patent number: 4966440
    Abstract: A hologram which comprises a light transparent base having coated thereon a hydrophilic water-swellable layer which contains the holographic image and a dye whose peak absorption is below the peak replay wavelength of the hologram. The hologram is produced by adding the dye after exposure of the hologram.
    Type: Grant
    Filed: March 22, 1989
    Date of Patent: October 30, 1990
    Assignee: Ilford Limited
    Inventors: David W. Butcher, Stephen R. Post