Patents by Inventor Radoslav Danilak

Radoslav Danilak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200057642
    Abstract: A methodology for populating an instruction word for simultaneous execution of instruction operations by a plurality of ALUs in a data path is provided. The methodology includes: creating a dependency graph of instruction nodes, each instruction node including at least one instruction operation; first selecting a first available instruction node from the dependency graph; first assigning the selected first available instruction node to the instruction word; second selecting any available dependent instruction nodes that are dependent upon a result of the selected first available instruction node and do not violate any predetermined rule; second assigning to the instruction word the selected any available dependent instruction nodes; and updating the dependency graph to remove any instruction nodes assigned during the first and second assigning from further consideration for assignment.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 20, 2020
    Applicant: TACHYUM LTD.
    Inventor: Radoslav DANILAK
  • Publication number: 20200057645
    Abstract: A methodology for preparing a series of instruction operations for execution by plurality of arithmetic logic units (ALU) is provided. The methodology includes first assigning a first instruction operation to the first ALU; first determining, for a second instruction operation having an input that depends directly on an output of a first instruction operation, whether all inputs for the second instruction operation are available within a locally predefined range from the first ALU; second assigning, in response to at least a positive result of the first determining, the second instruction operation to the second ALU; in response to a negative result of the first determining: ensuring a pause of at least one clock cycle will occur between execution of the first instruction operation and the second instruction operation; and third assigning the second instruction operation to an ALU of the plurality of ALUs.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 20, 2020
    Applicant: TACHYUM LTD.
    Inventor: Radoslav DANILAK
  • Publication number: 20190310934
    Abstract: Techniques are described for accessing data from a storage device. In one example, the storage device may include a storage medium comprising non-volatile memory, a network connection, and one or more processing entities. The one or more processors may be configured to receive a request from the network connection at the non-volatile memory storage device for accessing data associated with a file system object, the request comprising a virtual address offset, a file object identifier and a size of the data access, perform, at a flash translation layer of a storage device software stack executing on the one or more processing entities of the storage device, a translation from the virtual address offset to a physical address for the data stored on the non-volatile memory, using the virtual address offset and the file object identifier, and access the data from the physical address from the storage medium.
    Type: Application
    Filed: June 25, 2019
    Publication date: October 10, 2019
    Inventors: Radoslav DANILAK, Amit BOTHRA, Arvind PRUTHI
  • Patent number: 10380014
    Abstract: Techniques are described for accessing data from a storage device. In one example, the storage device may include a storage medium comprising non-volatile memory, a network connection, and one or more processing entities. The one or more processors may be configured to receive a request from the network connection at the non-volatile memory storage device for accessing data associated with a file system object, the request comprising a virtual address offset, a file object identifier and a size of the data access, perform, at a flash translation layer of a storage device software stack executing on the one or more processing entities of the storage device, a translation from the virtual address offset to a physical address for the data stored on the non-volatile memory, using the virtual address offset and the file object identifier, and access the data from the physical address from the storage medium.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 13, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Radoslav Danilak, Amit Bothra, Arvind Pruthi
  • Patent number: 10318181
    Abstract: Methods, systems and computer-readable storage media for increasing spare space in a storage subsystem including a flash memory, extending a lifetime of the storage subsystem to achieve a stored selected minimum lifetime based at least in part as a result of the increasing spare space, and identifying at least one aspect associated with the lifetime of the storage subsystem. The storage subsystem may include compressed data stored in the flash memory.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak
  • Patent number: 10282121
    Abstract: A translation system can translate a storage request to a physical address using fields as keys to traverse a map of nodes with node entries. A node entry can include a link to a next node or a physical address. Using a portion of the key as noted in node metadata, a node entry can be determined. When adding node entries to a node, a node utilization can exceed a threshold value. A new node can be created such that node entries are split between the original and new node. Node metadata of the parent node, new node and original node can be revised to identify which parts of the key are used to identify a node entry. When removing node entries from a node, node utilization can cross a minimum threshold value. Node entries from the node can be merged with a sibling, or the map can be rebalanced.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: May 7, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Radoslav Danilak, Ladislav Steffko, Qi Wu
  • Patent number: 10230406
    Abstract: A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.
    Type: Grant
    Filed: January 11, 2015
    Date of Patent: March 12, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Hao Zhong, Yan Li, Radoslav Danilak, Earl T. Cohen
  • Publication number: 20180329633
    Abstract: The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises allocating at least one block of memory selected from a subset of blocks to be written in accordance with an equalizing technique to equalize a variation between blocks of memory based on at least one factor. The method further comprises resupplying the subset of blocks.
    Type: Application
    Filed: February 21, 2018
    Publication date: November 15, 2018
    Inventor: Radoslav Danilak
  • Patent number: 10101937
    Abstract: A translation system can translate a storage request having multiple fields to a physical address using the fields as keys to traverse a map. The map can be made of nodes that include one or more node entries. The node entries can be stored in a hashed storage area or sorted storage area of a node. A hashed storage area can enable a quick lookup of densely addressed information by using a portion of the key to determine a location of a node entry. A sorted storage area can enable compact storage of sparse information by storing node entries that currently exist and allowing the entries to be searched. By offering both types of storage in a node, a node can be optimized for both dense and sparse information. A node entry can include a link to a next node or the physical address for the storage request.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 16, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Radoslav Danilak, Ladislav Steffko, Qi Wu
  • Patent number: 10037158
    Abstract: Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. Techniques are described for vertically integrating the various software functions and hardware functions for accessing storage hardware. In some embodiments, the system is implemented using non-volatile memory.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: July 31, 2018
    Assignee: Skyera, LLC
    Inventor: Radoslav Danilak
  • Patent number: 9921761
    Abstract: The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises allocating at least one block of memory selected from a subset of blocks to be written in accordance with an equalizing technique to equalize a variation between blocks of memory based on at least one factor. The method further comprises resupplying the subset of blocks.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: March 20, 2018
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak
  • Patent number: 9901010
    Abstract: A rack mountable 1U storage unit includes a plurality of memory modules arranged in two groups. The storage unit also has control circuitry. The memory modules have a dedicated exhaust channel to draw heat away from the memory modules. The exhaust channel for the memory modules is disposed over and is physically separated from the exhaust channel for the control circuitry. The storage unit can accommodate up to 42 memory modules due to a unique method of placing the individual memory modules.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: February 20, 2018
    Assignee: Skyera, LLC
    Inventors: Pinchas Herman, William Radke, Radoslav Danilak
  • Patent number: 9891675
    Abstract: In various embodiments, a high-density solid-state storage unit includes a base section and a cassette section having plurality of flash cards. The cassette section can be removably attached to the base section to provide security of data stored on the plurality of flash cards. The cassette section provides for physical security of the flash cards in part through packaging of the enclosure and energy transfer to the base station. The cassette section further provides for security of the data stored on the flash cards in part through a trusted platform module (TPM) embodied as a removable module connected to a universal serial bus (USB) style connector.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: February 13, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Pinchas Herman, William Radke, Radoslav Danilak
  • Publication number: 20170364308
    Abstract: Methods, apparatus, and systems, for interfacing one or more storage devices with a plurality of bridge chips. An apparatus may include a memory, a communication bus coupled to a device, and a processor communicatively coupled to the communication bus and the memory. The processor may be configured to implement storage traffic between a storage device and a central processor via a first storage port of a first bridge chip of a plurality of bridge chips. The processor may be further configured to multiplex, by the first bridge chip, the storage traffic to at least one bridge chip of the plurality of bridge chips, and distribute data across the plurality of bridge chips to produce a data distribution enabling each of the bridge chips to communicate with each other.
    Type: Application
    Filed: August 30, 2017
    Publication date: December 21, 2017
    Inventors: Ross John Stenfort, Radoslav Danilak
  • Publication number: 20170351605
    Abstract: Techniques are described for accessing data from a storage device. In one example, the storage device may include a storage medium comprising non-volatile memory, a network connection, and one or more processing entities. The one or more processors may be configured to receive a request from the network connection at the non-volatile memory storage device for accessing data associated with a file system object, the request comprising a virtual address offset, a file object identifier and a size of the data access, perform, at a flash translation layer of a storage device software stack executing on the one or more processing entities of the storage device, a translation from the virtual address offset to a physical address for the data stored on the non-volatile memory, using the virtual address offset and the file object identifier, and access the data from the physical address from the storage medium.
    Type: Application
    Filed: April 17, 2017
    Publication date: December 7, 2017
    Inventors: Radoslav Danilak, Amit Bothra, Arvind Pruthi
  • Publication number: 20170344303
    Abstract: A translation system can translate a request having multiple fields to a physical address using the fields as indexes to a multi-dimensional graph. A field or portion of a field can represent a location along an axis. When combined together, the fields can represent a point in n-space, where n is the number of axes. In some embodiments, a nearest neighbor calculation can be sufficient along an axis. Therefore, a point in n-space defined by the fields can be translated along an axis until a nearest neighbor entry is determined. When the entry is determined, the entry can be accessed to determine a correct response to the translation request.
    Type: Application
    Filed: March 14, 2017
    Publication date: November 30, 2017
    Inventors: Radoslav DANILAK, Ladislav STEFFKO, Qi WU
  • Patent number: 9823872
    Abstract: A translation system can translate a storage request having multiple fields to a physical address using the fields as keys to traverse a map. By using a map table, multiple storage services can be condensed into a single map traversal. The map can be made of nodes that include one or more node entries. The node entries can be stored in a hashed storage area or sorted storage area of a node. A node entry of root nodes or inner nodes can include a link to a next node. A node entry of a leaf node can include a physical address. Using the request fields as a key to a node, a node entry can be determined. A pointer in a root node entry or inner node entry can be followed to a next node. A physical address in a leaf node can be the translation of the storage request.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: November 21, 2017
    Assignee: Skyera, LLC
    Inventors: Radoslav Danilak, Ladislav Steffko, Qi Wu
  • Patent number: 9804794
    Abstract: The present disclosure relates to techniques for providing data redundancy after reducing memory writes. In one example implementation according to aspects of the present disclosure, a storage system receives a storage command for providing data redundancy in accordance with a first data redundancy scheme. The storage system then implements a subsequent data redundancy in accordance with a second data redundancy scheme.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: October 31, 2017
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak
  • Patent number: 9802124
    Abstract: A translation system can translate a storage request to a physical address using fields as keys to traverse a map of nodes with node entries. A node entry can include a link to a next node or a physical address. Using a portion of the key as noted in node metadata, a node entry can be determined. When snapshotting a dataset, a snapshot value can be updated in a root node entry. New data can be added under the new snaphsot value, preventing overwriting of the prior data, providing deduplication and quick snapshotting. When cloning a dataset, a new root node entry can be made for the clone. The new root entry can reference the original root entry of the original dataset. Metadata of nodes of the clone branch can identify whether the current branch contains updated data or whether the data exists off of the original root entry.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 31, 2017
    Assignee: Skyera, LLC
    Inventors: Radoslav Danilak, Ladislav Steffko, Qi Wu
  • Patent number: 9792074
    Abstract: A system, method, and computer program product are provided for interfacing one or more storage devices with a plurality of bridge chips. One or more storage devices are provided. Additionally, a plurality of bridge chips are provided. Furthermore, at least one multiplexing device is provided for interfacing the one or more storage devices with the plurality of bridge chips.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: October 17, 2017
    Assignee: Seagate Technology LLC
    Inventors: Ross John Stenfort, Radoslav Danilak