Patents by Inventor Radoslav Danilak

Radoslav Danilak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9286176
    Abstract: A solid state drive (SSD), includes: a plurality of solid state memory devices, each solid state memory device including a plurality of memory blocks arranged in a plurality of planes; a storage; and an SSD controller configured to: write data to memory blocks in a predefined sequence, detect a defective memory block in the plurality of solid state memory devices, mark the detected memory block as defective and store an address of a next non-defective memory block, and in response to data to be written to the marked memory block, the controller skips the marked memory block and writes the data to the next non-marked memory block.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: March 15, 2016
    Assignees: Western Digital Technologies, Inc., Skyera, LLC
    Inventors: Andrew J. Tomlin, Justin Jones, Rodney N. Mullendore, Radoslav Danilak
  • Publication number: 20160062684
    Abstract: A method including increasing spare space in a storage subsystem including a flash memory, wherein the storage subsystem includes compressed data stored in the flash memory; extending a lifetime of the storage subsystem to achieve a stored selected minimum lifetime, based at least in part as a result of the increasing spare space; identifying at least one aspect associated with the lifetime of the storage subsystem; and delaying, based at least upon one identified aspect, at least one operation that reduces the lifetime of the storage subsystem, wherein the delaying at least one operation includes delaying a command that initiates the at least one operation.
    Type: Application
    Filed: November 9, 2015
    Publication date: March 3, 2016
    Inventor: Radoslav Danilak
  • Patent number: 9268682
    Abstract: A data storage device comprises a plurality of non-volatile memory devices storing physical pages, each stored at a predetermined physical location. A controller may be coupled to the memory devices and configured to access data stored in a plurality of logical pages (L-Pages), each associated with an L-Page number that enables the controller to logically reference data stored in the physical pages. A volatile memory may comprise a logical-to-physical address translation map that enables the controller to determine a physical location, within the physical pages, of data stored in each L-Page. The controller may be configured to maintain, in the memory devices, journals defining physical-to-logical correspondences, each journal covering a predetermined range of physical pages and comprising a plurality of entries that associate one or more physical pages to each L-Page. The controller may read the journals upon startup and rebuild the address translation map from the read journals.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: February 23, 2016
    Assignees: Skyera, LLC, Western Digital Technologies, Inc.
    Inventors: Andrew J. Tomlin, Rodney N. Mullendore, Justin Jones, Radoslav Danilak
  • Publication number: 20160041790
    Abstract: A data storage system includes: non-volatile solid state memory including non-volatile storage units and a temporary register; a data storage controller configured to receive a write command including a plurality of logical segments of data from a host; a write buffer allocated to receive a portion of the plurality of logical segments of data and accumulate a physical segment of data corresponding to a write unit of the solid state memory; a solid state memory controller configured to transmit the accumulated data from the write buffer to the temporary storage register each time the write buffer accumulates a physical segment of data. The data storage controller acknowledges completion of the write command to the host after the last logical segment of data is written to the write buffer; and deallocates the write buffer after the solid state memory completes reception of the accumulated data into the temporary storage register.
    Type: Application
    Filed: October 20, 2015
    Publication date: February 11, 2016
    Inventors: Justin JONES, Andrew J. TOMLIN, Rodney N. MULLENDORE, Radoslav DANILAK
  • Publication number: 20160026528
    Abstract: The present disclosure relates to techniques for providing data redundancy after reducing memory writes. In one example implementation according to aspects of the present disclosure, a storage controller receives a storage command for providing data redundancy in accordance with a first data redundancy scheme. The storage controller then translates the storage command for providing the data redundancy in accordance with a second data redundancy scheme.
    Type: Application
    Filed: August 7, 2015
    Publication date: January 28, 2016
    Inventor: Radoslav Danilak
  • Publication number: 20160011974
    Abstract: The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises determining whether to reclaim one or more blocks of a memory. The method further comprises allocating at least one of the blocks to be written in accordance with the equalizing, in response to the determining, and selected from a subset of the blocks, wherein a respective lifetime factor is below a threshold set prior to the allocating.
    Type: Application
    Filed: September 23, 2015
    Publication date: January 14, 2016
    Inventor: Radoslav Danilak
  • Publication number: 20160011800
    Abstract: The present disclosure relates to examples of reducing memory write operations using coalescing memory buffers. In one example implementation according to aspects of the present disclosure, a method comprises computing a difference between a current state of data of at least one block of a storage device to which data is to be written and a state that would result from the write operation. The method further comprises populating at least one of one or more coalescing memory buffers with difference information associated with the difference and to be used to update an associated one of the blocks. Additionally, the method comprises selectively writing the difference information in the coalescing memory buffers to the storage devices, based on a determination of fullness of the coalescing memory buffers. The coalescing memory buffers are separate from the storage devices.
    Type: Application
    Filed: September 23, 2015
    Publication date: January 14, 2016
    Inventor: Radoslav Danilak
  • Patent number: 9229855
    Abstract: Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. In certain example embodiments, an active/active fault-tolerant storage device comprising two or more controllers may be implemented. In one aspect, each controller may have two or more processing entities for distributing the processing of the I/O requests. In one embodiment, the configuration of the components, modules and the controller board may be arranged in a manner to enhance heat dissipation, reduce power consumption, spread the power and work load, and reduce latency. In one embodiment, each controller may be coupled to the non-volatile memory (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as the Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: January 5, 2016
    Assignee: Skyera, LLC
    Inventors: Radoslav Danilak, William Radke
  • Patent number: 9183133
    Abstract: A system, method, and computer program product are provided for extending a lifetime of memory. In operation, spare space in memory is increased. Additionally, a lifetime of the memory is extended, as a result of increasing the spare space in the memory.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: November 10, 2015
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak
  • Patent number: 9177638
    Abstract: A data storage device may comprise a plurality of Multi-Level Cell (MLC) non-volatile memory devices comprising a plurality of lower pages and a corresponding plurality of higher-order pages. A controller may be configured to write data to and read data from the plurality of lower pages and the corresponding plurality of higher-order pages. A buffer may be coupled to the controller, which may be configured to accumulate data to be written to the MLC non-volatile memory devices, allocate space in the buffer and write the accumulated data to the allocated space. At least a portion of the accumulated data may be written in a lower page of the MLC non-volatile memory devices and the space in the buffer that stores data written to the lower page may be de-allocated when all higher-order pages corresponding to the lower page have been written in the MLC non-volatile memory devices.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: November 3, 2015
    Assignees: Western Digital Technologies, Inc., Skyera, LLC
    Inventors: Radoslav Danilak, Rodney N. Mullendore, Andrew J. Tomlin, Justin Jones, Jui-Yao Yang
  • Patent number: 9170742
    Abstract: A system, method, and computer program product are provided for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information associated with the difference is stored in the memory. To this end, the write operations may be reduced, utilizing the difference information.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: October 27, 2015
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak
  • Patent number: 9170939
    Abstract: A data storage system includes: non-volatile solid state memory including non-volatile storage units and a temporary register; a data storage controller configured to receive a write command including a plurality of logical segments of data from a host; a write buffer allocated to receive a portion of the plurality of logical segments of data and accumulate a physical segment of data corresponding to a write unit of the solid state memory; a solid state memory controller configured to transmit the accumulated data from the write buffer to the temporary storage register each time the write buffer accumulates a physical segment of data. The data storage controller acknowledges completion of the write command to the host after the last logical segment of data is written to the write buffer; and deallocates the write buffer after the solid state memory completes reception of the accumulated data into the temporary storage register.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 27, 2015
    Assignees: Western Digital Technologies, Inc., Skyera, LLC
    Inventors: Justin Jones, Andrew J. Tomlin, Rodney N. Mullendore, Radoslav Danilak
  • Patent number: 9165682
    Abstract: In operation, respective lifetime expectancy scores are calculated for each of a plurality of blocks of a memory based on a respective count percentage of free space of each of the blocks. The blocks are recycled based on at least some of the life expectancy scores. A total amount of the blocks that are re-written is minimized while equalizing lifetime expectancy score variation between the blocks.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: October 20, 2015
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak
  • Patent number: 9128872
    Abstract: A storage subsystem receives writes via a storage subsystem interface and reduces a number of the writes. Data associated with the reduced number of writes is stored in storage devices of a single drive. Computed redundancy information is stored in the storage devices. A data redundancy scheme is implemented via a disk controller that is enabled to operate without a loss of data in the presence of at least a single failure of any of the storage devices.
    Type: Grant
    Filed: May 11, 2014
    Date of Patent: September 8, 2015
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak
  • Patent number: 9059736
    Abstract: A data storage device may comprise a flash controller and an array of flash memory devices coupled to the flash controller. The array may comprise a plurality of S-Pages that may each comprise a plurality of F-Pages. In turn, each of the plurality of F-Pages may be configured to store a variable amount of data and a variable amount of error correction code. The flash controller may be configured to generate an error correction code across each F-Page of an S-Page and to store the generated error correction code within one or more F-Pages having the largest amount of data.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: June 16, 2015
    Assignees: Western Digital Technologies, Inc., Skyera, Inc.
    Inventors: Radoslav Danilak, Rodney N. Mullendore, Justin Jones, Andrew J. Tomlin
  • Publication number: 20150138716
    Abstract: In various embodiments, a high-density solid-state storage unit includes a base section and a cassette section having plurality of flash cards. The cassette section can be removably attached to the base section to provide security of data stored on the plurality of flash cards. The cassette section provides for physical security of the flash cards in part through packaging of the enclosure and energy transfer to the base station. The cassette section further provides for security of the data stored on the flash cards in part through a trusted platform module (TPM) embodied as a removable module connected to a universal serial bus (USB) style connector.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: Skyera, Inc.
    Inventors: Pinchas Herman, William Radke, Radoslav Danilak
  • Publication number: 20150138717
    Abstract: In various embodiments, a high-density solid-state storage unit includes a base section and a cassette section having plurality of flash cards. The cassette section can be removably attached to the base section to provide security of data stored on the plurality of flash cards. The cassette section provides for physical security of the flash cards in part through packaging of the enclosure and energy transfer to the base station. The cassette section further provides for security of the data stored on the flash cards in part through a trusted platform module (TPM) embodied as a removable module connected to a universal serial bus (USB) style connector.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: Skyera, Inc.
    Inventors: Pinchas Herman, William Radke, Radoslav Danilak
  • Publication number: 20150134880
    Abstract: Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. In certain example embodiments, an active/active fault-tolerant storage device comprising two or more controllers may be implemented. In one aspect, each controller may have two or more processing entities for distributing the processing of the I/O requests. In one embodiment, the configuration of the components, modules and the controller board may be arranged in a manner to enhance heat dissipation, reduce power consumption, spread the power and work load, and reduce latency. In one embodiment, each controller may be coupled to the non-volatile memory (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as the Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Applicant: Skyera, Inc.
    Inventors: Radoslav Danilak, William Radke
  • Publication number: 20150134881
    Abstract: Various systems, methods, apparatuses, and computer-readable media. for accessing a storage device are described. In certain example embodiments, an active/active fault tolerant storage device comprising two or more controllers may be implemented. In one embodiment, each controller may be coupled to the non-volatile memory (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Applicant: Skyera, Inc.
    Inventors: Radoslav Danilak, William Radke
  • Patent number: 9021339
    Abstract: A data storage system configured to implement a data reliability scheme is disclosed. In one embodiment, a data storage system controller detects uncorrectable errors using intra page parity when data units are read from a set of pages. When an uncorrectable error is detected, the data storage system controller attempts to recover user data using inter page parity without using all data from each page of the set of pages. Recovery of user data can thereby be performed without reading all data from each page. As a result, the amount of time needed to read data can be reduced in some cases and overall data storage system performance can be increased.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: April 28, 2015
    Assignees: Western Digital Technologies, Inc., Skyera, Inc.
    Inventors: Guangming Lu, Leader Ho, Radoslav Danilak, Rodney N. Mullendore, Justin Jones, Andrew J. Tomlin