Abstract: In various embodiments, a high-density solid-state storage unit includes a plurality of flash cards. Each flash card has a flash controller that incorporates one or more resources for facilitating compression and decompression operations. In one aspect, data reduction and data reconstruction operations can be performed in-line as data is stored to and retrieved from flash memory. In another aspect, data reduction and data reconstruction operations can be performed as a service. Any one of the plurality of flash cards can be used to provide data reduction or data reconstruction services on demand for any type of data, including system data, libraries, and firmware code.

Abstract: The present disclosure relates to examples of reducing memory write operations using coalescing memory buffers. In one example implementation according to aspects of the present disclosure, a method comprises computing a difference between a current state of data of at least one block of a storage device to which data is to be written and a state that would result from a write operation. The method further comprises populating at least one coalescing memory buffer with difference information associated with the difference and to be used to update an associated block of the storage device.

Abstract: A translation system can translate a storage request to a physical address using fields as keys to traverse a map of nodes with node entries. A node entry can include a link to a next node or a physical address. Using a portion of the key as noted in node metadata, a node entry can be determined. When adding node entries to a node, a node utilization can exceed a threshold value. A new node can be created such that node entries are split between the original and new node. Node metadata of the parent node, new node and original node can be revised to identify which parts of the key are used to identify a node entry. When removing node entries from a node, node utilization can cross a minimum threshold value. Node entries from the node can be merged with a sibling, or the map can be rebalanced.

Abstract: Methods, systems and computer-readable storage media for increasing spare space in a storage subsystem including a flash memory, extending a lifetime of the storage subsystem to achieve a stored selected minimum lifetime based at least in part as a result of the increasing spare space, and identifying at least one aspect associated with the lifetime of the storage subsystem. The storage subsystem may include compressed data stored in the flash memory.

Abstract: The present disclosure relates to examples of reducing memory write operations using coalescing memory buffers. In one example implementation according to aspects of the present disclosure, a method comprises computing a difference between a current state of data of at least one block of a storage device to which data is to be written and a state that would result from the write operation. The method further comprises populating at least one of one or more coalescing memory buffers with difference information associated with the difference and to be used to update an associated one of the blocks. Additionally, the method comprises selectively writing the difference information in the coalescing memory buffers to the storage devices, based on a determination of fullness of the coalescing memory buffers. The coalescing memory buffers are separate from the storage devices.

Abstract: Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. Techniques are described for vertically integrating the various software functions and hardware functions for accessing storage hardware. In some embodiments, the system is implemented using non-volatile memory.

Abstract: A plurality of software programmable processors is disclosed. The software programmable processors are controlled by rotating circular buffers. A first processor and a second processor within the plurality of software programmable processors are individually programmable. The first processor within the plurality of software programmable processors is coupled to neighbor processors within the plurality of software programmable processors. The first processor sends and receives data from the neighbor processors. The first processor and the second processor are configured to operate on a common instruction cycle. An output of the first processor from a first instruction cycle is an input to the second processor on a subsequent instruction cycle.

Abstract: A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.

Abstract: Various systems, methods, apparatuses, and computer-readable media, for accessing a storage device are described. In certain example embodiments, an active/active fault tolerant storage device comprising two or more controllers may be implemented. In one embodiment, each controller may be coupled to the non-volatile memory’ (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.

Abstract: A method including increasing spare space in a storage subsystem including a flash memory, wherein the storage subsystem includes compressed data stored in the flash memory; extending a lifetime of the storage subsystem to achieve a stored selected minimum lifetime, based at least in part as a result of the increasing spare space; identifying at least one aspect associated with the lifetime of the storage subsystem; and delaying, based at least upon one identified aspect, at least one operation that reduces the lifetime of the storage subsystem, wherein the delaying at least one operation includes delaying a command that initiates the at least one operation.

Abstract: Techniques are described for accessing data from a storage device. In one example, the storage device may include a storage medium comprising non-volatile memory, a network connection, and one or more processing entities. The one or more processors may be configured to receive a request from the network connection at the non-volatile memory storage device for accessing data associated with a file system object, the request comprising a virtual address offset, a file object identifier and a size of the data access, perform, at a flash translation layer of a storage device software stack executing on the one or more processing entities of the storage device, a translation from the virtual address offset to a physical address for the data stored on the non-volatile memory, using the virtual address offset and the file object identifier, and access the data from the physical address from the storage medium.

Abstract: A translation system can translate a storage request to a physical address using fields as keys to traverse a map of nodes with node entries. A node entry can include a link to a next node or a physical address. Using a portion of the key as noted in node metadata, a node entry can be determined. When adding node entries to a node, a node utilization can exceed a threshold value. A new node can be created such that node entries are split between the original and new node. Node metadata of the parent node, new node and original node can be revised to identify which parts of the key are used to identify a node entry. When removing node entries from a node, node utilization can cross a minimum threshold value. Node entries from the node can be merged with a sibling, or the map can be rebalanced.

Abstract: In various embodiments, a high-density solid-state storage unit includes a base section and a cassette section having plurality of flash cards. The cassette section can be removably attached to the base section to provide security of data stored on the plurality of flash cards. The cassette section provides for physical security of the flash cards in part through packaging of the enclosure and energy transfer to the base station. The cassette section further provides for security of the data stored on the flash cards in part through a trusted platform module (TPM) embodied as a removable module connected to a universal serial bus (USB) style connector.

Abstract: The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises allocating at least one block of memory selected from a subset of blocks to be written in accordance with an equalizing technique to equalize a variation between blocks of memory based on at least one factor. The method further comprises resupplying the subset of blocks.

Abstract: A translation system can translate a request having multiple fields to a physical address using the fields as indexes to a multi-dimensional graph. A field or portion of a field can represent a location along an axis. When combined together, the fields can represent a point in n-space, where n is the number of axes. In some embodiments, a nearest neighbor calculation can be sufficient along an axis. Therefore, a point in n-space defined by the fields can be translated along an axis until a nearest neighbor entry is determined. When the entry is determined, the entry can be accessed to determine a correct response to the translation request.

Abstract: Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. Techniques are described for vertically integrating the various software functions and hardware functions for accessing storage hardware. In some embodiments, the system is implemented using non-volatile memory.

Abstract: A processing device is provided. A cluster includes a plurality of groups of processing elements. A multi-word device is connected to the processing elements within the groups. Each processing element in a particular group is in communication with all other processing elements within the particular group, and only one of the processing elements within other groups in the cluster. Each processing element is limited to operations in which input bits can be processed and an output obtained without reference to other bits. The multi-word device is configured to cooperate with at least two other processing elements to perform processing that requires reference to other bits to obtain a result.

Abstract: A rack mountable 10U storage unit includes a plurality of memory modules arranged in multiple rows. The storage unit also has control circuitry. Each of the memory modules have multiple heating zones and a heat spreader coupled to it. The memory modules may have heat spreaders having differing thermal dissipation capacity coupled to them. The storage unit can accommodate up to 120 memory modules due to a unique method of placing the individual memory modules.

Abstract: The present disclosure relates to techniques for providing data redundancy after reducing memory writes. In one example implementation according to aspects of the present disclosure, a storage system receives a storage command for providing data redundancy in accordance with a first data redundancy scheme. The storage system then implements a subsequent data redundancy in accordance with a second data redundancy scheme.

Abstract: A mass storage memory device is disclosed. The device includes a nonvolatile memory, a volatile memory configured to store logical to physical (L2P) data associating logical addresses of data stored in the nonvolatile memory with physical locations of the nonvolatile memory at which the data is stored, and a controller. The controller writes L2P data in the nonvolatile memory so the L2P data can be preserved through a power failure. The controller also writes L2P data stored in the nonvolatile memory to the volatile memory to rebuild the L2P table.