Abstract: An extensible iterative multiplier design is provided. Embodiments provide cascaded 8-bit multipliers for simplifying the performance of multi-byte multiplications. Booth encoding is performed in the lowest order multiplier, with the result of the Booth encoding then provided to higher order multipliers. Additionally, multiply-add operations can be performed by initializing a partial product sum register. Configurable connections between the multipliers facilitate a variety of possible multiplication options, including the possibility of varying the width of the operands.

Abstract: A mass storage memory device is disclosed. The device includes a plurality of blades where two blades are used to store parity data corresponding to data stored in the other blades. The device also includes a controller configured to write data to the blades along stripes extending from the other blades to the two blades, where the parity data within a stripe is based on the data written to the other blades in the stripe, and wherein the parity data includes two or more types of parity data.

Abstract: A data storage device may comprise an array of flash memory devices comprising a plurality of blocks, each comprising a plurality of physical pages. A controller may be coupled to and configured to program and read data from the array responsive to host commands. The controller may be configured to store data in a plurality of logical pages (L-Pages) of different sizes, each associated with an L-Page number that is configured to enable the host to logically reference data stored in one or more of the physical pages; and maintain a logical-to-physical address translation map configured to enable the controller to determine a location, within one or more physical pages, of the data referenced by each L-Page number. The translation map may comprise a plurality of mapping entries arranged by L-Page numbers, each comprising a complete starting physical address of an L-Page within one of the physical pages.

Abstract: Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. In certain example embodiments, an active/active fault-tolerant storage device comprising two or more controllers may be implemented. In one aspect, each controller may have two or more processing entities for distributing the processing of the I/O requests. In one embodiment, the configuration of the components, modules and the controller board may be arranged in a manner to enhance heat dissipation, reduce power consumption, spread the power and work load, and reduce latency. In one embodiment, each controller may be coupled to the non-volatile memory (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as the Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.

Abstract: The present disclosure relates to techniques for providing data redundancy after reducing memory writes. In one example implementation according to aspects of the present disclosure, a storage controller receives a storage command for providing data redundancy in accordance with a first data redundancy scheme. The storage controller then translates the storage command for providing the data redundancy in accordance with a second data redundancy scheme.

Abstract: The present disclosure relates to techniques for providing data redundancy after reducing memory writes. In one example implementation according to aspects of the present disclosure, a storage controller receives a storage command for providing data redundancy in accordance with a first data redundancy scheme. The storage controller then translates the storage command for providing the data redundancy in accordance with a second data redundancy scheme.

Abstract: The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises determining whether to reclaim one or more blocks of a memory. The method further comprises allocating at least one of the blocks to be written in accordance with the equalizing, in response to the determining, and selected from a subset of the blocks, wherein a respective lifetime factor is below a threshold set prior to the allocating.

Abstract: A data storage system includes: non-volatile solid state memory including non-volatile storage units and a temporary register; a data storage controller configured to receive a write command including a plurality of logical segments of data from a host; a write buffer allocated to receive a portion of the plurality of logical segments of data and accumulate a physical segment of data corresponding to a write unit of the solid state memory; a solid state memory controller configured to transmit the accumulated data from the write buffer to the temporary storage register each time the write buffer accumulates a physical segment of data. The data storage controller acknowledges completion of the write command to the host after the last logical segment of data is written to the write buffer; and deallocates the write buffer after the solid state memory completes reception of the accumulated data into the temporary storage register.

Abstract: Various systems, methods, apparatuses, and computer-readable media, for accessing a storage device are described. In certain example embodiments, an active/active fault tolerant storage device comprising two or more controllers may be implemented. In one embodiment, each controller may be coupled to the non-volatile memory’ (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.

Abstract: The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises determining whether to reclaim one or more blocks of a memory. The method further comprises allocating at least one of the blocks to be written in accordance with the equalizing, in response to the determining, and selected from a subset of the blocks, wherein a respective lifetime factor is below a threshold set prior to the allocating.

Abstract: In various embodiments, a high-density solid-state storage unit includes a base section and a cassette section having plurality of flash cards. The cassette section can be removably attached to the base section to provide security of data stored on the plurality of flash cards. The cassette section provides for physical security of the flash cards in part through packaging of the enclosure and energy transfer to the base station. The cassette section further provides for security of the data stored on the flash cards in part through a trusted platform module (TPM) embodied as a removable module connected to a universal serial bus (USB) style connector.

Abstract: Accessing data of varying-sized quanta in non-volatile memory provides improved storage efficiency in some situations. For example, a Solid-State Disk (SSD) controller receives (e.g. uncompressed) data from a computing host (e.g. a disk write command), compresses the data, and stores the compressed data into non-volatile (e.g. flash) memory. In response to a subsequent request from the host (e.g. a disk read command), the SSD controller reads and uncompresses the compressed data from the memory. The compressed data is stored in the memory according to varying-sized quanta, due to, e.g., compression algorithm, operating mode, and compression effectiveness on various data. The SSD controller uncompresses the data in part by consulting an included map table to locate header(s) stored in the memory, parsing the header(s) to locate appropriate (compressed) data stored in the memory, and uncompressing the appropriate data from the memory to produce the uncompressed data.

Abstract: A rack mountable 1U storage unit includes a plurality of memory modules arranged in two groups. The storage unit also has control circuitry. The memory modules have a dedicated exhaust channel to draw heat away from the memory modules. The exhaust channel for the memory modules is disposed over and is physically separated from the exhaust channel for the control circuitry. The storage unit can accommodate up to 42 memory modules due to a unique method of placing the individual memory modules.

Abstract: Adaptive ECC techniques for use with flash memory enable improvements in flash memory lifetime, reliability, performance, and/or storage capacity. The techniques include a set of ECC schemes with various code rates and/or various code lengths (providing different error correcting capabilities), and error statistic collecting/tracking (such as via a dedicated hardware logic block). The techniques further include encoding/decoding in accordance with one or more of the ECC schemes, and dynamically switching encoding/decoding amongst one or more of the ECC schemes based at least in part on information from the error statistic collecting/tracking (such as via a hardware logic adaptive codec receiving inputs from the dedicated error statistic collecting/tracking hardware logic block). The techniques further include selectively operating a portion (e.g., page, block) of the flash memory in various operating modes (e.g. as an MLC page or an SLC page) over time.

Abstract: An integrated networked storage and switching apparatus comprises one or more flash memory controllers, a system controller, and a network switch integrated within a common chassis. The integration of storage and switching enables the components to share a common power supply and temperature regulation system, achieving efficient use of available space and power, and eliminating added complexity of external cables between the switch a storage devices. Additionally, the architecture enables substantial flexibility and optimization of network traffic policies for both network and storage-related traffic.

Abstract: Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. In certain example embodiments, an active/active fault tolerant storage device comprising two or more controllers may be implemented. In one embodiment, each controller may be coupled to the non-volatile memory (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.

Abstract: The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises determining whether to reclaim one or more blocks of a memory. The method further comprises allocating at least one of the blocks to be written in accordance with the equalizing, in response to the determining, and selected from a subset of the blocks, wherein a respective lifetime factor is below a threshold set prior to the allocating.

Abstract: Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. In certain example embodiments, an active/active fault-tolerant storage device comprising two or more controllers may be implemented. In one aspect, each controller may have two or more processing entities for distributing the processing of the I/O requests. In one embodiment, the configuration of the components, modules and the controller board may be arranged in a manner to enhance heat dissipation, reduce power consumption, spread the power and work load, and reduce latency. In one embodiment, each controller may be coupled to the non-volatile memory (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as the Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.

Abstract: In various embodiments, a high-density solid-state storage unit includes a base section and a cassette section having plurality of flash cards. The cassette section can be removably attached to the base section to provide security of data stored on the plurality of flash cards. The cassette section provides for physical security of the flash cards in part through packaging of the enclosure and energy transfer to the base station. The cassette section further provides for security of the data stored on the flash cards in part through a trusted platform module (TPM) embodied as a removable module connected to a universal serial bus (USB) style connector.

Abstract: A rack mountable 1U storage unit includes a plurality of memory modules arranged in two groups. The storage unit also has control circuitry. The memory modules have a dedicated exhaust channel to draw heat away from the memory modules. The exhaust channel for the memory modules is disposed over and is physically separated from the exhaust channel for the control circuitry. The storage unit can accommodate up to 42 memory modules due to a unique method of placing the individual memory modules.