Abstract: An electronic substrate may be formed having at least one metal-to-dielectric adhesion promotion material layer therein. The electronic substrate may comprise a conductive metal trace, a dielectric material layer on the conductive metal trace, and the adhesion promotion material layer between the conductive metal trace and the dielectric material layer, wherein the adhesion promotion material layer comprises an organic adhesion material and a metal constituent dispersed within the organic adhesion material, wherein a metal within the metal constituent has a standard reduction potential greater than a standard reduction potential of the conductive metal trace.

Abstract: Embodiments described herein are directed to interfacial layers and techniques of forming such interfacial layers. An interfacial layer having one or more light absorbing molecules is on a metal layer. The light absorbing molecule(s) may comprise a moiety exhibiting light absorbing properties. The interfacial layer can assist with improving adhesion of a resist layer to the metal layer and with improving use of one or more lithography techniques to fabricate interconnects and/or features using the resist and metal layers for a package substrate, a semiconductor package, or a PCB. For one embodiment, the interfacial layer includes, but is not limited to, an organic interfacial layer. Examples of organic interfacial layers include, but are not limited to, self-assembled monolayers (SAMs), constructs and/or variations of SAMs, organic adhesion promotor moieties, and non-adhesion promoter moieties.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

Abstract: The present disclosure is directed to an electroless plating process using a panel basket for holding semiconductor panels comprising a plurality of metal pads and shielding the metal pads from contaminants and over-etching and under-etching caused by the contaminants.

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes light-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises an interposer, where the interposer comprises a cavity that passes through the interposer, a through interposer via (TIV), and an interposer pad electrically coupled to the TIV. In an embodiment, the electronic package further comprises a nested component in the cavity, where the nested component comprises a component pad, and a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect. In an embodiment, the first interconnect and the second interconnect each comprise an intermediate pad, and a bump over the intermediate pad.

Abstract: An integrated circuit package may be formed comprising a substrate that includes a mold material layer and a signal routing layer, wherein the mold material layer comprises at least one bridge and at least one foam structure embedded in a mold material. In one embodiment, the substrate may include the mold material of the mold material layer filling at least a portion of cells within the foam structure. In a further embodiment, at least two integrated circuit devices may be attached to the substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a monolayer having a plurality of first molecules over the first surface of the package substrate. In an embodiment, the first molecules each comprise a first functional group attached to the first surface, and a first release moiety attached to the first functional group.

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first layer of a package substrate and a conductive trace over the first layer of the package substrate. In an embodiment, the conductive trace comprises a conductive body with a first surface over the first layer of the package substrate, a second surface opposite the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, the second surface has a first roughness and the sidewall surfaces have a second roughness that is less than the first roughness.

Abstract: An interconnection structure is disclosed. The interconnection structure includes a dielectric layer, an interfacial TiC layer on the dielectric layer, the interfacial TiC layer having a uniform thickness, and a Ti layer on the TiC layer.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.