Patents by Inventor Rahul Manepalli

Rahul Manepalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190393183
    Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes alight-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Suddhasattwa NAD, Rahul MANEPALLI, Marcel WALL
  • Publication number: 20190320537
    Abstract: Embodiments described herein are directed to interfacial layers and techniques of forming such interfacial layers. An interfacial layer having one or more light absorbing molecules is on a metal layer. The light absorbing molecule(s) may comprise a moiety exhibiting light absorbing properties. The interfacial layer can assist with improving adhesion of a resist layer to the metal layer and with improving use of one or more lithography techniques to fabricate interconnects and/or features using the resist and metal layers for a package substrate, a semiconductor package, or a PCB. For one embodiment, the interfacial layer includes, but is not limited to, an organic interfacial layer. Examples of organic interfacial layers include, but are not limited to, self-assembled monolayers (SAMs), constructs and/or variations of SAMs, organic adhesion promotor moieties, and non-adhesion promoter moieties.
    Type: Application
    Filed: April 16, 2018
    Publication date: October 17, 2019
    Inventors: Suddhasattwa NAD, Rahul MANEPALLI, Marcel WALL
  • Patent number: 8569108
    Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 29, 2013
    Assignee: Intel Corporation
    Inventors: Dingying Xu, Leonel R. Arana, Nachiket R. Raravikar, Mohit Mamodia, Rajasekaran Swaminathan, Rahul Manepalli
  • Patent number: 8377550
    Abstract: Methods and associated structures of forming underfill material are described. Those methods may include applying an underfill to an interconnect structure comprising residue from a no clean flux, wherein the underfill comprises at least one of a functionalized nanofiller and a micron-sized filler.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: February 19, 2013
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Hong Dong, Sandeep Razdan, Nisha Ananthakrisnan, Rahul Manepalli
  • Publication number: 20130017650
    Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 17, 2013
    Inventors: Dingying Xu, Leonel R. Arana, Nachiket R. Raravikar, Mohit Mamodia, Rajasekaran Swaminathan, Rahul Manepalli
  • Patent number: 8287996
    Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Dingying Xu, Leonel R. Arana, Nachiket R. Raravikar, Mohit Mamodia, Rajasekaran Swaminathan, Rahul Manepalli
  • Publication number: 20110159228
    Abstract: Methods and associated structures of forming underfill material are described. Those methods may include applying an underfill to an interconnect structure comprising residue from a no clean flux, wherein the underfill comprises at least one of a functionalized nanofiller and a micron-sized filler.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Inventors: Rajasekaran Swaminathan, Hong Dong, Sandeep Razdan, Nisha Ananthakrishana, Rahul Manepalli
  • Publication number: 20110151624
    Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 23, 2011
    Inventors: Dingying Xu, Leonel R. Arana, Nachiket R. Raravikar, Mohit Mamodia, Rajasekaran Swaminathan, Rahul Manepalli
  • Publication number: 20070152314
    Abstract: A stacked die package comprises a first die on a substrate, a die attach layer superjacent to the first die, and a second die on the die attach layer. The die attach layer comprises a die attach material having a glass transition temperature substantially in the range of 150-180° C. Raising the glass transition temperature reduces the mismatch in the coefficients of thermal expansion (CTE) between the die attach and the mold compound that surrounds the first die in the package.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: Rahul Manepalli, Amram Eitan, Prasanna Raghavan
  • Publication number: 20070132086
    Abstract: An integrated circuit device includes a die having an interconnect structure formed over a surface thereof. A volume of compliant material located within the interconnect structure underlies one or more bond pads disposed on an uppermost layer of the interconnect structure. The compliant material may absorb stresses exerted on the interconnect structure during assembly, testing, or subsequent operation. Other embodiments are described and claimed.
    Type: Application
    Filed: December 13, 2005
    Publication date: June 14, 2007
    Inventors: Sairam Agraharam, Rahul Manepalli
  • Publication number: 20070111375
    Abstract: A shock load applied to a solder ball may be cushioned by providing a viscoelastic material in association with the solder ball. The viscoelastic material dampens shock loads applied to the solder ball and reduces the rate of failure between the solder ball and the rest of the package.
    Type: Application
    Filed: November 15, 2005
    Publication date: May 17, 2007
    Inventors: Rahul Manepalli, Sairam Agraharam
  • Patent number: 7202304
    Abstract: An underfill material is presented that may be used between an electrical component and a substrate. The underfill material may be a cured epoxy resin composition comprising a liquid or semisolid epoxy resin and a polyfunctional anhydride polymer and/or oligomer curing agent. The use of anhydride polymers and/or oligomers decrease the volatilization of the composition, thereby reducing the porosity of the underfill material. By changing substituents of the anhydride polymer and/or oligomer, the underfill material may be designed to modify viscosity, decrease moisture adsorption, volatilization and modulus, improve mechanical properties, and enhance adhesion.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventors: Saikumar Jayaraman, Rahul Manepalli
  • Publication number: 20060154080
    Abstract: An underfill material is presented that may be used between an electrical component and a substrate. The underfill material may be a cured epoxy resin composition comprising a liquid or semisolid epoxy resin and a polyfunctional anhydride polymer and/or oligomer curing agent. The use of anhydride polymers and/or oligomers decrease the volatilization of the composition, thereby reducing the porosity of the underfill material. By changing substituents of the anhydride polymer and/or oligomer, the underfill material may be designed to modify viscosity, decrease moisture adsorption, volatilization and modulus, improve mechanical properties, and enhance adhesion.
    Type: Application
    Filed: March 8, 2006
    Publication date: July 13, 2006
    Inventors: Saikumar Jayaraman, Rahul Manepalli
  • Publication number: 20060141749
    Abstract: A package includes a flexible substrate with a first region and a second region, an encapsulated die supported by the first region, and a conformable fold adhesive introduced between the encapsulated die and the flexible substrate. The second region of the flexible substrate is folded over the surface of the encapsulated die.
    Type: Application
    Filed: February 21, 2006
    Publication date: June 29, 2006
    Inventors: Rahul Manepalli, Karen Paghasian, Shinobu Kourakata, Ruel Aranda
  • Patent number: 7041736
    Abstract: An underfill material is presented that may be used between an electrical component and a substrate. The underfill material may be a cured epoxy resin composition comprising a liquid or semisolid epoxy resin and a polyfunctional anhydride polymer and/or oligomer curing agent. The use of anhydride polymers and/or oligomers decrease the volatilization of the composition, thereby reducing the porosity of the underfill material. By changing substituents of the anhydride polymer and/or oligomer, the underfill material may be designed to modify viscosity, decrease moisture adsorption, volatilization and modulus, improve mechanical properties, and enhance adhesion.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventors: Saikumar Jayaraman, Rahul Manepalli
  • Publication number: 20060073624
    Abstract: A die-attach composition includes a resin such as a thermosetting resin, a hardener, and a low molecular weight oligomer diluent. A die-attach composition includes a polyimide in a major amount and a resin such as a thermosetting resin in a minor amount. The die-attach composition also includes a reactive polymer diluent. Combinations of the low molecular weight oligomer diluent and the reactive polymer diluent are included. The die-attach composition is applied to surface mount technology such as wire-bond dice. A computing system is also included that uses the die-attach composition.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 6, 2006
    Inventors: Rahul Manepalli, Ravindra Tanikella
  • Publication number: 20060038276
    Abstract: A method for producing a multiple-die device by attaching a die to a substrate using a first die-attach material having a first processing temperature and attaching a subsequent die using a second die-attach material having a second processing temperature such that the process of attaching the second die does not degrade the first die-attach material. For one embodiment, multiple dies are attached using each die-attach material. For one embodiment, the first die-attach material is a thermoplastic film and the second and subsequent die-attach materials are reformulations of the thermoplastic film.
    Type: Application
    Filed: October 19, 2005
    Publication date: February 23, 2006
    Inventors: Rahul Manepalli, Shinobu Kourakata, Nina Ricci Buenaseda
  • Publication number: 20060033192
    Abstract: A method for producing a multiple-die device by attaching a die to a substrate using a first die-attach material having a first processing temperature and attaching a subsequent die using a second die-attach material having a second processing temperature such that the process of attaching the second die does not degrade the first die-attach material. For one embodiment, multiple dies are attached using each die-attach material. For one embodiment, the first die-attach material is a thermoplastic film and the second and subsequent die-attach materials are reformulations of the thermoplastic film.
    Type: Application
    Filed: August 13, 2004
    Publication date: February 16, 2006
    Inventors: Rahul Manepalli, Shinobu Kourakata, Nina Ricci Buenaseda
  • Publication number: 20050224993
    Abstract: A package includes a flexible substrate with a first region and a second region, an encapsulated die supported by the first region, and a conformable fold adhesive introduced between the encapsulated die and the flexible substrate. The second region of the flexible substrate is folded over the surface of the encapsulated die.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Inventors: Rahul Manepalli, Karen Paghasian, Shinobu Kourakata, Ruel Aranda
  • Patent number: 6794225
    Abstract: Embodiments of the methods of the present invention provide a Molded Matrix Array Package (MMAP) carrier substrate panel that prevents underfill wetting in the inter-die areas. Surface treatments are provided via plasmas and/or patterned chemical depositions that reduce the surface free energy of the inter-die area to below the surface free energy of the underfill material. The surface treatments prevent the underfill material from wetting the carrier substrate panel and therefore encroachment upon the inter-die area. This provides a underfill material-free inter-die area allowing adhesion between the mold compound and carrier substrate.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: September 21, 2004
    Assignee: Intel Corporation
    Inventors: Rahul Manepalli, Terry Sterrett, Tian-an Chen, Vassoudevane Lebonheur