Abstract: Disclosed herein are IC structures that implement field plates for III-N transistors in a form of electrically conductive structures provided in a III-N semiconductor material below the polarization layer (i.e., at the “backside” of an IC structure). In some embodiments, such a field plate may be implemented as a through-silicon via (TSV) extending from the back/bottom face of the substrate towards the III-N semiconductor material. Implementing field plates at the backside may provide a viable approach to changing the distribution of electric field at a transistor drain and increasing the breakdown voltage of an III-N transistor without incurring the large parasitic capacitances associated with the use of metal field plates provided above the polarization material. In addition, backside field plates may serve as a back barrier for advantageously reducing drain-induced barrier lowering.

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

Abstract: IC structures that include transmission line structures to be integrated with III-N devices are disclosed. An example transmission line structure includes a transmission line of an electrically conductive material provided above a stack of a III-N semiconductor material and a polarization material. The transmission line structure further includes means for reducing electromagnetic coupling between the line and charge carriers present below the interface of the polarization material and the III-N semiconductor material. In some embodiments, said means include a shield material of a metal or a doped semiconductor provided over portions of the polarization material that are under the transmission line. In other embodiments, said means include dopant atoms implanted into the portions of the polarization material that are under the transmission line, and into at least an upper portion of the III-N semiconductor material under such portions of the polarization material.

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

Abstract: Group-III nitride (III-N) tunnel devices with a device structure including multiple quantum wells. A bias voltage applied across first device terminals may align the band structure to permit carrier tunneling between a first carrier gas residing in a first of the wells to a second carrier gas residing in a second of the wells. A III-N tunnel device may be operable as a diode, or further include a gate electrode. The III-N tunnel device may display a non-linear current-voltage response with negative differential resistance, and be employed as a frequency mixer operable in the GHz and THz bands. In some examples, a GHz-THz input RF signal and local oscillator signal are coupled into a gate electrode of a III-N tunnel device biased within a non-linear regime to generate an output RF signal indicative of a frequency difference between the RF signal and a local oscillator signal.

Abstract: Disclosed herein are IC structures, packages, and devices that include linearization devices integrated on the same support structure as III-N transistors. A linearization device may be any suitable device that may exhibit behavior complementary to that of a III-N transistor so that a combined behavior of the III-N transistor and the linearization device includes less nonlinearity than the behavior of the III-N transistor alone. Linearization devices may be implemented as, e.g., one-sided diodes, two-sided diodes, or P-type transistors. Integrating linearization devices on the same support structure with III-N transistors advantageously provides an integrated solution based on III-N transistor technology, thus providing a viable approach to reducing or eliminating nonlinear behavior of III-N transistors.

Abstract: A device structure includes a first gate on a first fin, a second gate on a second fin, where the second gate is spaced apart from the first gate by a distance. A fuse spans the distance and is in contact with the first gate and the second gate. A first dielectric is between the first fin and the second fin, where the first dielectric is in contact with, and below, the fuse and a second dielectric is between the first gate and the second gate, where the second dielectric is on the fuse.

Abstract: Embodiments disclosed herein include a semiconductor device and methods of forming such a device. In an embodiment, the semiconductor device comprises a substrate and a transistor on the substrate. In an embodiment, the transistor comprises a first gate electrode, where the first gate electrode is part of a first array of gate electrodes with a first pitch. In an embodiment, the first gate electrode has a first average grain size. In an embodiment, the semiconductor device further comprises a component cell on the substrate. In an embodiment, the component cell comprises a second gate electrode, where the second gate electrode is part of a second array of gate electrodes with a second pitch that is larger than the first pitch. In an embodiment, the second gate electrode has a second average grain size that is larger than the first average grain size.

Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

Abstract: A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a source, a drain, and a semiconductor channel between the source and the drain. In an embodiment, the semiconductor channel has a non-uniform strain through a thickness of the semiconductor channel. In an embodiment, the semiconductor device further comprises a gate stack around the semiconductor channel.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a substrate, a source region over the substrate, a drain region over the substrate, and a semiconductor body extending from the source region to the drain region. In an embodiment, the semiconductor body has a first region with a first conductivity type and a second region with a second conductivity type. In an embodiment, the semiconductor device further comprises a gate structure over the first region of the semiconductor body, where the gate structure is closer to the source region than the drain region.

Abstract: Embodiments disclosed herein include nanoribbon and nanowire semiconductor devices. In an embodiment, the semiconductor device comprises a nanowire disposed above a substrate. In an embodiment, the nanowire has a first dopant concentration, and the nanowire comprises a pair of tip regions on opposite ends of the nanowire. In an embodiment, the tip regions comprise a second dopant concentration that is greater than the first dopant concentration. In an embodiment, the semiconductor device further comprises a gate structure over the nanowire. In an embodiment, the gate structure is wrapped around the nanowire, and the gate structure defines a channel region of the device. In an embodiment, a pair of source/drain regions are on opposite sides of the gate structure, and both source/drain regions contact the nanowire.

Abstract: Embodiments disclosed herein include nanowire and nanoribbon devices with non-uniform dielectric thicknesses. In an embodiment, the semiconductor device comprises a substrate and a plurality of first semiconductor layers in a vertical stack over the substrate. The first semiconductor layers may have a first spacing. In an embodiment, a first dielectric surrounds each of the first semiconductor layers, and the first dielectric has a first thickness. The semiconductor device may further comprise a plurality of second semiconductor layers in a vertical stack over the substrate, where the second semiconductor layers have a second spacing that is greater than the first spacing. In an embodiment a second dielectric surrounds each of the second semiconductor layers, and the second dielectric has a second thickness that is greater than the first thickness.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, the semiconductor device comprises a substrate, and a first transistor over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel above the substrate, a first gate dielectric surrounding the first semiconductor channel, and a first gate electrode over the first gate dielectric. In an embodiment, the semiconductor device further comprises a second transistor over the substrate. In an embodiment, the second transistor comprises a second semiconductor channel above the substrate, a second gate dielectric surrounding the second semiconductor channel, where the second gate dielectric is different than the first gate dielectric, and a second gate electrode over the second gate dielectric, where the first gate electrode and the second gate electrode comprise the same material.