Patents by Inventor Raj Kumar

Raj Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200402051
    Abstract: In an aspect, a computing system is configured to: send, to a transfer rail server, a request for stored card data associated with a value transfer card; receive stored card data identifying an entity having a stored representation of the value transfer card; provide user interface data to a client device, the user interface data causing the client device to display a user interface that includes an entity listing that is based on the stored card data, the user interface including a selectable option to add an entity-based control to the identified entity; receive, from the client device, an instruction to apply an entity-based control to an identified one of the entities in the stored card data; and in response to receiving the instruction to apply the entity-based control, implement the entity-based control to affect use of the value transfer card by the identified entity and not affect use of the value transfer card by other entities.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Applicant: The Toronto-Dominion Bank
    Inventor: Raj Kumar Choudhary
  • Publication number: 20200402027
    Abstract: In an aspect, a computing system is configured to: obtain, from a transfer rail server, stored card data, the stored card data identifying one or more entities having a stored representation of a value transfer card; obtain, from the transfer rail server, data indicating a time of last use of the value transfer card by one or more of the identified entities; identify a dormant entity based on the data indicating the time of last use of the value transfer card by the one or more of the identified entities; send, to a client device associated with the value transfer card, a notification providing a prompt to disable the value transfer card for the dormant entity; receive a command; and disable the value transfer card for the dormant entity to prevent further use of the value transfer card by the dormant entity.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Applicant: The Toronto-Dominion Bank
    Inventor: Raj Kumar Choudhary
  • Publication number: 20200393792
    Abstract: A method for optimally producing a holographic image using a Holographic Optical Element (HOE) and the HOE meant for controlling directions and divergences of light beams to impart system compactness. The system uses concave and convex lenses and other beam expanding, splitting, modulating and combining optics for realization of compactness and high throughput. The thin laser beam is split using a holographic optical element and a conventional beam splitter. A neutral density filter adjusts the intensity of a reference beam to match the intensity of an object beam so that high quality digital holograms can be recorded. Effects of vibrations are minimized by the compact optical design, by anti-vibration mounts, by mounting all the opto-mechanical components on a single rigid platform and by enclosing the system. An electro-optical sensor array records holograms digitally and an algorithm numerically reconstructs and further quantifies the results using a personal computer/laptop/tablet etc.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 17, 2020
    Applicant: COUNCIL OF SCIENTIFIC AND INDUSTRIAL RESEARCH
    Inventors: Raj KUMAR, Gaurav DWIVEDI, Omendra SINGH
  • Publication number: 20200395444
    Abstract: A method for depositing a phosphorus doped silicon arsenide film is disclosed. The method may include, providing a substrate within a reaction chamber, heating the substrate to a deposition temperature, exposing the substrate to a silicon precursor, an arsenic precursor, and a phosphorus dopant precursor, and depositing the phosphorus doped silicon arsenide film over a surface of the substrate. Semiconductor device structures including a phosphorus doped silicon arsenide film deposited by the methods of the disclosure are also provided.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 17, 2020
    Inventors: Chi-Wei Lo, Alexandros Demos, Raj Kumar
  • Patent number: 10797133
    Abstract: A method for depositing a phosphorus doped silicon arsenide film is disclosed. The method may include, providing a substrate within a reaction chamber, heating the substrate to a deposition temperature, exposing the substrate to a silicon precursor, an arsenic precursor, and a phosphorus dopant precursor, and depositing the phosphorus doped silicon arsenide film over a surface of the substrate. Semiconductor device structures including a phosphorus doped silicon arsenide film deposited by the methods of the disclosure are also provided.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 6, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Chi-Wei Lo, Alexandros Demos, Raj Kumar
  • Publication number: 20200303081
    Abstract: A method of calculating blast injury metrics in a weapon training/IED blast scene can include: reconstructing topological layout of the scene having at least one real subject and a blast source; obtaining anthropometric and posture data for each real subject; obtaining anatomical soldier model for each real subject; identifying real position of at least one real pressure sensor on each soldier during a blast; positioning a virtual sensor on each anatomical soldier model to correspond with real pressure sensor on the real subject; calculating weapon signature of the blast source, the weapon signature including pressure versus time for a blast from the blast source; generating simulated pressure traces on each anatomical soldier model at east virtual pressure sensor; calculating blast injury metrics for the at least one real subject; and generating a report that includes the blast injury metrics for the at least one real subject.
    Type: Application
    Filed: November 26, 2019
    Publication date: September 24, 2020
    Inventors: Andrzej Przekwas, Harsha T. Garimella, Timothy Zehnbauer, Zhijian Chen, Vincent Harrand, Raj Kumar Gupta, Gary Kamimori, Walter Carr
  • Publication number: 20200288576
    Abstract: A method is provided for forming a printed circuit board (PCB) assembly. The method may include drilling a first plurality of vias having a first diameter in a PCB and filling the first plurality of vias to form a first plurality of plated or filled vias. The method may also include drilling a second plurality of vias having a second diameter in the PCB, and filling the second plurality of vias to form a second plurality of plated or filled vias. The first plurality of plated or filled vias is mixed with the second plurality of plated or filled vias such that the spacing between the first plurality of plated or filled vias and the second plurality of plated or filled vias is less than the first diameter and the second diameter.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 10, 2020
    Inventors: Michael LEN, Chong MEI, Michael LUGERT, Raj KUMAR
  • Patent number: 10740715
    Abstract: In some examples, a computing device may receive, from a first user device, a communication indicating a request to create a combined order for items offered by one or more merchants. For example, the combined order may enable a plurality of users to independently purchase individual ones of the items from the one or more merchants. The combined order may be created having an initial condition and may be accessible by the plurality of users for adding items to the combined order. At least one selection of a respective item may be received from each user of the plurality of users. For instance, each selection may change the condition of the combined order. In addition, the computing device may process the items added to the combined order as a single order to perform at least one action.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 11, 2020
    Assignee: DOORDASH, INC.
    Inventors: Abhay Raj Kumar, Jesse Lee Reiss, Ajit Kalidindi Varma, Matthew Rhodes, Richard David Din, Anthony Bishopric
  • Publication number: 20200225955
    Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N?1), and the branch history in table T(N?1) is of greater length than the branch history of table T(N?2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 16, 2020
    Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
  • Publication number: 20200202575
    Abstract: Objects can be rendered in three dimensions and viewed and manipulated in an augmented reality environment. A number of object images, a number of segmentation masks, and an object mesh structure are used by a client device to render the object in three dimensions. The object images and segmentation masks can be sequenced into frames. The object images and segmentation masks can be partitioned into patches and sequenced, or ordered, within each patch, and a keyframe can be assigned in each patch. Then, the object images and segmentation masks can be encoded into video files and sent to a client device. The client device can quickly retrieve a requested object image and segmentation mask based at least in part on identifying the keyframe in the same patch as the object image and segmentation mask.
    Type: Application
    Filed: March 3, 2020
    Publication date: June 25, 2020
    Inventors: Arnab Sanat Kumar Dhua, Neil Raj Kumar, Karl Hillesland, Radek Grzeszczuk, Scott Paul Robertson
  • Publication number: 20200182967
    Abstract: Monitoring vibrations induced on non-rotational components, of a machine is a key requirement to ensure that the machine is well within safe operational limits. Existing approaches are sensor based and may not be practical in many practical scenarios with extreme environments. Embodiments herein provide method and system for monitoring machine health using radar based segregation for induced machine vibrations. The method provides model free a data driven approach wherein a micro Doppler signal captured by the RADAR placed in proximity of a target machine is processed and analyzed in accordance with a Wide Band Frequency Spectrum (WBFS) to estimate a rotational frequency and a translational frequency of induced machine vibrations in the target machine. Further, apply a rule engine on the estimated rotational frequency and the translational frequency to provide an alert notification to an end user when the induced machine vibrations cross the defined machine standards.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 11, 2020
    Applicant: Tata Consultancy Services Limited
    Inventors: Raj Kumar RAKSHIT, Ranjan DASGUPTA, Tapas CHAKRAVARTY
  • Publication number: 20200143101
    Abstract: Provided is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of integrated circuit device. The method can further include determining target gates referred to as trace signals within integrated circuit device. The method can further include creating hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving the scalability of connectivity verification by utilizing hierarchical decomposition embodiment of the invention.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: Pradeep Kumar Nalla, Raj Kumar Gajavelly, Jason Baumgartner, Raja Bilwakeshwar Ivaturi
  • Patent number: 10633572
    Abstract: The present invention discloses a process for the dissociation of natural gas hydrates comprises injecting additives or hydrate dissociation promoters into the system at the hydrate dissociation temperatures ranging from 283-293 K in conjunction with or without first depressurizing the system to pressures (50%-75%) below the hydrate equilibrium pressure and such leading to the recovery of methane or natural gases.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: April 28, 2020
    Assignees: Council of Scientific & Industrial Research, Gail (India) Limited
    Inventors: Rajnish Kumar, Sudip Roy, Gaurav Bhattacharjee, Nilesh Choudhary, Asheesh Kumar, Raj Kumar Kashyap, Parivesh Chugh, Nawal Kishore Pande
  • Patent number: 10621297
    Abstract: A computing system determines a first set of registers having constant next-state functions in the netlist. The computing system identifies an observable gate in fan-out of a register in the first set, wherein an observable gate is a gate that is critical to a verification or synthesis context. The computing system identifies a second set of reducible registers in the fan-in of the observable gate. The computing system modifies at least one of an initial value and a next-state function of at least one reducible register of the second set to reflect an observable value of the at least one reducible register observed at the observable gate. The computing system simplifies one or more logic gates implementing the observable gate and the fan-in of the observable gate by eliminating a reference to a constant next-state function register in the first set of registers.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Coporation
    Inventors: Jason R. Baumgartner, Robert L. Kanzelman, Pradeep Kumar Nalla, Raj Kumar Gajavelly, Dheeraj Baby
  • Patent number: 10618883
    Abstract: Compounds of formula A-I and B-I, compositions comprising the compounds, methods of making the compounds and methods of their uses are disclosed.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: April 14, 2020
    Assignee: Celgene Corporation
    Inventors: Matthew D. Alexander, Matthew D. Correa, Joshua Hansen, Raj Kumar Raheja, John Sapienza
  • Publication number: 20200104434
    Abstract: A computing system determines a first set of registers having constant next-state functions in the netlist. The computing system identifies an observable gate in fan-out of a register in the first set, wherein an observable gate is a gate that is critical to a verification or synthesis context. The computing system identifies a second set of reducible registers in the fan-in of the observable gate. The computing system modifies at least one of an initial value and a next-state function of at least one reducible register of the second set to reflect an observable value of the at least one reducible register observed at the observable gate. The computing system simplifies one or more logic gates implementing the observable gate and the fan-in of the observable gate by eliminating a reference to a constant next-state function register in the first set of registers.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Jason R. BAUMGARTNER, Robert L. KANZELMAN, Pradeep Kumar NALLA, Raj Kumar GAJAVELLY, Dheeraj BABY
  • Patent number: 10593066
    Abstract: Objects can be rendered in three dimensions and viewed and manipulated in an augmented reality environment. A number of object images, a number of segmentation masks, and an object mesh structure are used by a client device to render the object in three dimensions. The object images and segmentation masks can be sequenced into frames. The object images and segmentation masks can be partitioned into patches and sequenced, or ordered, within each patch, and a keyframe can be assigned in each patch. Then, the object images and segmentation masks can be encoded into video files and sent to a client device. The client device can quickly retrieve a requested object image and segmentation mask based at least in part on identifying the keyframe in the same patch as the object image and segmentation mask.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: March 17, 2020
    Assignee: A9.COM, INC.
    Inventors: Arnab Sanat Kumar Dhua, Neil Raj Kumar, Karl Hillesland, Radek Grzeszczuk, Scott Paul Robertson
  • Patent number: 10579770
    Abstract: Invention disclosed herein is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of the integrated circuit device. The method can further include determining target gates referred to as trace signals within the integrated circuit device. The method can further include creating a hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving scalability of the connectivity verification by utilizing hierarchical decomposition embodiment of the invention.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradeep Kumar Nalla, Raj Kumar Gajavelly, Jason Baumgartner, Raja Bilwakeshwar Ivaturi
  • Patent number: 10566999
    Abstract: A coded signal is received via a physical channel. The coded signal is encoded by a parity check matrix. In some examples, the coded signal is low density parity check-encoded. The coded signal is decoded to determine a result signal. Said decoding alternatingly updates, for each one of a number of iterations, bit node values representing bits of the result signal and check node values representing constrains of the parity check matrix. In some examples, the decoding determines the result signal at a first precision and updates at least partly at a second precision which is lower than the first precision. In further examples, the number of iterations is dynamically adjusted.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: February 18, 2020
    Assignee: Lantiq Beteiligungs-GmbH & Co. KG
    Inventors: Raj Kumar Jain, Ravindra Singh
  • Patent number: 10540468
    Abstract: A logic verification program, method and system provide an efficient behavior when verifying large logic designs. The logic is partitioned by cut-nodes that dominate two or more RANDOMS and a check is performed for a given cut-node to determine whether any of the dominated RANDOMS can be merged to a constant by performing satisfiability checks with each RANDOM merged to a constant, to determine whether a range of output values for the given cut-node has been reduced by merging the RANDOM. If the range is not reduced, the RANDOM can be added to the set of merge-able RANDOMS along with the corresponding constant value. If the range has been reduced, the opposite constant value is tried for a node and if the range is reduced for both constants, then the cut-node is abandoned for merging that dominated RANDOM and the next dominated RANDOM is tried.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Raj Kumar Gajavelly, Jason R. Baumgartner, Robert L. Kanzelman, Alexander Ivrii, Pradeep Kumar Nalla