PACKAGE-ON-PACKAGE INTERCONNECT STIFFENER
Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
This is a Continuation application of Ser. No. 12/384,984 filed Apr. 10, 2009, which is presently pending.
FIELDEmbodiments of the invention relate to semiconductor packaging technology. More particularly, embodiments of the invention relate to a package-on-package interconnect stiffener.
BACKGROUNDMobile devices such as mobile phones, mobile internet devices (MIDs) and laptops, are designed with smaller form factor and slimmer profile for improved aesthetic and functional appeals. The size of and real estate occupied by semiconductor packages in the devices need to be scaled down accordingly. Package-on-package (PoP) packaging technology is employed to stack a semiconductor package on top of another semiconductor package to remove the x and y dimensions constraints in the layout of semiconductor packages on a motherboard.
PoP technology presents various problems, particularly with respect to the original equipment manufacturer (OEM) process. One of the problems is the limitation of cold surface to cold surface solder reflow process.
Another problem typically associated with PoP packaging is the coefficient of thermal expansion (CTE) mismatch between top device package 100 and bottom device package 150. The CTE mismatch is due to the fact that top device package 100 and bottom device package 150 are made from different materials and undergo different rates of thermal expansion in an elevated temperature range. The different rates of expansion and contraction result in warpage of the PoP assembly. Warpage of the PoP assembly presents process challenges in the package stacking process step and quality of joint formation between top device package 100 and bottom device package 150. Intrinsic stresses accumulated in the solder joints between the packages may risk quality and reliability failures during the use of the device.
Embodiments of the invention are illustrated by way of example and not limited in the figures of the accompanying drawings, in which like references indicate similar elements.
Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments include a planar stiffener having contact pads on the bottom side attached to a bottom device package, and contact pads on the top side of the stiffener to receive a top device package. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package. Embodiments of the invention provide reliable electrical interconnection and warpage control between the top device package and the bottom device package.
Stiffener 200 also includes conductive traces 600 fabricated in substrate 220 to electrically interconnect planar contact pads 210 on the top side of stiffener 220 with planar contact pads 240 on the bottom side of stiffener 220.
In operation 720 (
Embodiments of the invention provide a device package electrically interconnected with an interconnect stiffener upon which another device package can be mounted and electrically connected to form a package-on-package assembly. The stiffener in the package-on-package assembly provides the necessary stiffness to the assembly for improved warpage control and the platform on which a top device package can be attached with greater process control.
In the foregoing specification, reference has been made to specific embodiments of the invention. It will, however be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.
Claims
1. A package-on-package (PoP) assembly, comprising:
- a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
- a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and
- a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
2. The assembly of claim 1, wherein the stiffener includes routing features accommodating various circuitry designs of the second package.
3. The assembly of claim 2, wherein the substrate includes a coefficient of thermal expansion (CTE) approximately between 15 and 25 ppm, and a flexural modulus approximately between 15 and 30 GPa.
4. The assembly of claim 1, wherein the layout of the second plurality of planar contact pads of the stiffener matches the layout of the inter-package contact pads of the first package.
5. The assembly of claim 1, wherein the stiffener includes a plug material disposed between the first plurality and the second plurality of planar contact pads.
6. The assembly of claim 1, wherein the stiffener includes a plug material disposed in the substrate.
7. A method to form a package-on-package (PoP) assembly, comprising:
- providing a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
- attaching micro balls to the inter-package contact pads of the first package;
- connecting a planar stiffener to the micro balls attached to the first package, the stiffener having a first plurality of planar contact pads on the top side of the stiffener to receive a second semiconductor package, and a second plurality of planar contact pads to connect the stiffener to the micro balls attached to the first package; and
- reflowing the micro balls to form electrical connection between the stiffener and the first package.
8. The method of claim 7, further comprising attaching a bottom side of the stiffener to the first package by way of an adhesive of low glass transition temperature (Tg).
9. The method of claim 7, wherein the stiffener comprises:
- a substrate having a through recess adapted to house a die attached to the first package, and a plurality of through openings through which the first and second pluralities of contact pads are disposed;
- a solder-wettable planar surface finish on the first and second pluralities of contact pads; and
- a conductive trace electrically connecting the first plurality of contact pads to the corresponding second plurality of contact pads.
10. A semiconductor assembly, comprising:
- a first semiconductor package including a first substrate and a first die having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
- a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect the planar stiffener and a second die, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package and a wire bond in contact with the second die and electrically coupled to the first semiconductor package through the planar stiffener;
- wherein the second die and the planar stiffener are stacked on the first substrate.
11. The semiconductor assembly of claim 10, wherein the planar stiffener is configured to electrically connect a second semiconductor package including the planar stiffener and the second die.
12. The semiconductor assembly of claim 10, wherein the second die is part of a memory package.
13. The semiconductor assembly of claim 10, wherein the second die is part of a cache unit.
14. The semiconductor assembly of claim 10, wherein the second die is part of a device package suited for connection with the type of device of the first semiconductor package.
15. The semiconductor assembly of claim 10, wherein the first die is part of a semiconductor logic package.
16. The semiconductor assembly of claim 10, wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a memory package.
17. The semiconductor assembly of claim 10, wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a cache unit.
18. The semiconductor assembly of claim 10, wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a device package suited for connection with the type of device of the first semiconductor package.
19. The semiconductor assembly of claim 10, wherein the wire bond is electrically coupled to the planar stiffener by direct contact to a second substrate upon which the second die is disposed.
20. The semiconductor assembly of claim 10, wherein the first semiconductor package is attachable to a motherboard via the second level interconnect pads.
21. A semiconductor assembly, comprising:
- a first semiconductor package including a first substrate and a first die having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
- a stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect the planar stiffener and a second die, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package and
- a wire bond in contact with the second die and electrically coupled to the first semiconductor package through the stiffener;
- wherein the second die and the stiffener are stacked on the first substrate;
- wherein the stiffener is configured to electrically connect a second semiconductor package including the stiffener and the second die; and
- wherein the second die is part of a memory package.
22. The semiconductor assembly of claim 21, wherein the wire bond is electrically coupled to the stiffener by direct contact to a second substrate upon which the second die is disposed.
23. A semiconductor assembly, comprising:
- a first semiconductor package including a first substrate and a first die having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
- a stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect the planar stiffener and a second die, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package;
- a wire bond in contact with the second die and electrically coupled to the first semiconductor package through the stiffener;
- wherein the second die and the stiffener are stacked on the first substrate;
- wherein the stiffener is configured to electrically connect a second semiconductor package; and
- wherein the second die is part of a memory package; and
- wherein the first semiconductor package and the stiffener are electrically coupled through a micro ball.
24. The semiconductor assembly of claim 23, wherein the first die is part of a semiconductor logic package.
25. The semiconductor assembly of claim 23, wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a memory package.
26. The semiconductor assembly of claim 23, wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a cache unit.
27. The semiconductor assembly of claim 23, wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a device package suited for connection with the type of device of the first semiconductor package.
28. The semiconductor assembly of claim 23, wherein the wire bond is electrically coupled to the stiffener by direct contact to a second substrate upon which the second die is disposed.
29. A semiconductor assembly, comprising:
- a first semiconductor package including a first die and a first substrate having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
- a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect to a second semiconductor package, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package; and
- a wire bond that that is wire-bonded to a die in the second semiconductor package.
30. The semiconductor assembly of claim 29, wherein the second die is part of a memory package.
31. The semiconductor assembly of claim 29, wherein the second die is part of a cache unit.
32. The semiconductor assembly of claim 29, wherein the second die is part of a device package suited for connection with the type of device of the first package.
33. The semiconductor assembly of claim 29, wherein the first die is part of a semiconductor logic package.
34. The semiconductor assembly of claim 29, wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a memory package.
35. The semiconductor assembly of claim 29, wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a cache unit.
36. The semiconductor assembly of claim 29, wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a device package suited for connection with the type of device of the first package.
37. A semiconductor assembly, comprising:
- a first semiconductor package including a first substrate and a first die having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;
- a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect a second semiconductor package including the planar stiffener and a second die, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package; and
- a wire bond in contact with the second die and electrically coupled to the first semiconductor package through the planar stiffener; wherein the second die and the planar stiffener are stacked on the first substrate.
38. The semiconductor assembly of claim 37, wherein the second die is part of a memory package.
39. The semiconductor assembly of claim 37, wherein the second die is part of a cache unit.
40. The semiconductor assembly of claim 37, wherein the second die is part of a device package suited for connection with the type of device of the first package.
41. The semiconductor assembly of claim 37, wherein the first die is part of a semiconductor logic package.
42. The semiconductor assembly of claim 37, wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a memory package.
43. The semiconductor assembly of claim 37, wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a cache unit.
44. The semiconductor assembly of claim 37, wherein the first die is part of a semiconductor logic package, and wherein the second die is part of a device package suited for connection with the type of device of the first package.
Type: Application
Filed: Jul 10, 2013
Publication Date: Nov 7, 2013
Inventors: Sanka Ganesan (Chandler, AZ), Yosuke Kanaoka (Tsukuba-shi), Ram S. Viswanath (Phoenix, AZ), Rajasekaran Swaminathan (Tempe, AZ), Robert M. Nickerson (Chandler, AZ), Leonel R. Arana (Phoenix, AZ), John S. Guzek (Chandler, AZ), Yoshihiro Tomita (Tsukuba-shi)
Application Number: 13/939,146
International Classification: H01L 23/488 (20060101); H01L 21/50 (20060101);