Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: A traffic flow based map cache refresh may be provided. A computing device may receive a dropped packet message when a packet associated with a flow having a destination and a source was dropped before it reached the destination. Next, in response to receiving the dropped packet message, a map request message may be sent to a Map Server (MS). In response to sending the map request message, a map response message may be received indicating an updated destination for the flow. A map cache may then be refreshed for the source of the flow based on the updated destination from the received map response message.

Abstract: An adder uses with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are the same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals to the majority gates can be analog, digital, or a combination of them, which are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for a UE capability for AI/ML. A UE may receive a request from a network to report a UE capability for at least one of an AI procedure or an ML procedure. The UE may transmit to the network, based on the request to report the UE capability, an indication of one or more of an AI capability, an ML capability, a radio capability associated with the at least one of the AI procedure or the ML procedure, or a core network capability associated with the at least one of the AI procedure or the ML procedure.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a primary cell or a primary secondary cell (PSCell), configuration information for a conditional PSCell addition or change (CPAC), the configuration information indicating configurations for one or more candidate PSCells. The UE may detect a failure, associated with the conditional PSCell addition or change, associated with a first target PSCell from the one or more candidate PSCells. The UE may perform an action to recover the CPAC based at least in part on detecting the failure. Numerous other aspects are described.

Abstract: Services with policy control may be provided. A computing device may receive registration information associated with a border device. The registration information may comprise information identifying a service provided by a server associated with the border device, information identifying the border device, and policies associated with the service. Then an address for the server may be determined. Next a request may be received comprising the information identifying the service provided by the server. In response to receiving the request comprising the information identifying the service provided by the server, the address for the server, the information identifying the border device, and the policies associated with the service may be provided.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

Abstract: The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

Abstract: Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

Abstract: Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

Abstract: There is provided a system and for simultaneously displaying multiple graphical user interfaces via the same display. The multiple graphical user interfaces are hosted by one or more remote host controllers. A user device is in operative communication with the one or more remote host controllers and comprises an interface display for displaying one or more of the multiple graphical user interfaces. A system controller is in operative communication with the user display device. The system controller has a processor with an associated memory of processor executable code that when executed provides the controller with performing computer-implementable steps comprising separating the interface display in two or more interface display portions and selectively providing for two or more of the graphical user interfaces to be simultaneously displayed via respective ones of the two or more interface display portions.

Abstract: Techniques for automated configuration are provided. A first device detects a new device connected by one or more new links in a network, and the first device transmits, to a dynamic host configuration protocol (DHCP) server, a request for a first new subnet. The first device then assigns a first address of the first new subnet to a first new interface of the first device. The first device additionally transmits a second address of the first new subnet to the new device, where the new device uses the second address to establish connectivity to the network.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a network entity, a logged measurement configuration that defines an event for event triggered measurement logging, wherein the event is associated with a radio access technology (RAT)-specific coverage hole or a frequency specific coverage hole. The UE may perform, based at least in part on the logged measurement configuration, measurement logging based at least in part on an occurrence of the event associated with the RAT-specific coverage hole or the frequency specific coverage hole. Numerous other aspects are described.

Abstract: A method, apparatus, and computer program product are disclosed for facilitating two-way email communication in manner that obfuscates sender and recipient email addresses. The method includes receiving a correspondence request indication; assigning a first transaction address to a sender and a second transaction address to a recipient; receiving a message from the sender; associating the message from the sender with the first transaction address; and causing a transmission of the message from the sender to the recipient using the first transaction address. A corresponding apparatus and computer program product are also provided.

Abstract: Techniques are disclosed relating to the modification of data in a time-series data lake. For example, in various embodiments, the disclosed techniques include a cloud-based service that maintains a time-series data lake that includes, for an organization, a time-series representation of data from one or more of the organization's data sources. The cloud-based service may receive a request to modify data associated with a particular user of the organization. As a non-limiting example, this request may correspond to a “Right to Be Forgotten” request from the particular user. This request may include one or more search parameters and an indication of one or more modifications to be performed. Based on the request, the cloud-based service may parse the time-series data lake to identify a subset of data that matches the one or more search parameters and perform the requested modifications on the subset of data in the time-series data lake.

Abstract: An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.

Abstract: A method for integrating applications into a software suite is provided. The method includes: receiving a first code set that corresponds to a first application; obtaining an approval of the first code set; compiling the first code set in order to generate a module that is executable within the software suite; determining at least one target environment within the software suite for deployment of the first application; and deploying the executable module to each of the at least one target environment. An automated testing process and an automated validation process are applicable to deployed modules.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.