Abstract: A method may include bridging in, via a fabric, a multicast data packet from a source device to a first edge device of a plurality of edge devices and flooding the multicast data packet to the plurality of edge devices within a mutual subnetwork of the fabric. The method further includes bridging out the multicast data packet from a second edge device of the plurality of edge devices to a receiving device. The source device and the receiving device are located within the mutual subnetwork.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

Abstract: A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.

Abstract: Methods, systems, and devices for wireless communications are described for capability indications by a reduced capability user equipment (UE) and UE-based performance measurement parameter reporting or self-organizing network (SON) parameter reporting based on the capability indications. A reduced capability UE may transmit a set of capabilities to a base station that indicate various types of parameter reporting that are supported at the UE. The base station may identify the UE as a reduced capability device, and set one or more reporting parameters based on the indicated UE capabilities. The base station may provide a reporting configuration to the UE with the one or more reporting parameters, and the UE may provide reporting of measured parameters (e.g., performance measurement parameter reporting or SON parameter reporting) based on the reporting configuration.

Abstract: The disclosure relates in some aspects to enabling a user terminal (UT) to obtain information about nearby cells and any beams generated by nearby cells. For example, a network can send a neighbor cell list to UTs, where the list identifies the cells in that neighborhood and provides information about any beams generated by those cells. Thus, a UT can learn the neighboring beams/cells that the UT can reselect to if the current beam/cell becomes weak. In some aspects, the UE can learn the attitude (e.g., pitch, roll, yaw, or any combination thereof) profile of neighboring satellites as well as the pointing angles and the ON-OFF schedules of their beams. In some aspects, the UT can learn a start angle and a span for a satellite and use this information to identify a satellite the UT can reselect to if the current beam/cell becomes weak.

Abstract: Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

Abstract: Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric).

Abstract: Services with policy control may be provided. A computing device may receive registration information associated with a border device. The registration information may comprise information identifying a service provided by a server associated with the border device, information identifying the border device, and policies associated with the service. Then an address for the server may be determined. Next a request may be received comprising the information identifying the service provided by the server. In response to receiving the request comprising the information identifying the service provided by the server, the address for the server, the information identifying the border device, and the policies associated with the service may be provided.

Abstract: There is provided a system for modulating user commands via command input images displayed on a graphical user interface based on a user viewing direction relative to the displayed command input images and the graphical user interface. The system uses an image capturing device for capturing real time images of a user's face, eyes and irises and determines the eye orientation. The system separates the graphical user interface into interface portions and determines a correlation between the eye orientation and one or more portions to determine if any of the foregoing are viewed portions. The system determines whether a viewed portion contains a command input image and only allows user input commands via the command input image to be processed if the image is within a viewed portion.

Abstract: There is provided a system and for simultaneously displaying multiple graphical user interfaces via the same display. The multiple graphical user interfaces are hosted by one or more remote host controllers. A user device is in operative communication with the one or more remote host controllers and comprises an interface display for displaying one or more of the multiple graphical user interfaces. A system controller is in operative communication with the user display device. The system controller has a processor with an associated memory of processor executable code that when executed provides the controller with performing computer-implementable steps comprising separating the interface display in two or more interface display portions and selectively providing for two or more of the graphical user interfaces to be simultaneously displayed via respective ones of the two or more interface display portions.

Abstract: Automated techniques for converting network devices from a Layer 2 (L2) network into a Layer 3 (L3) network in a hierarchical manner are described herein. The network devices may be configured to boot such that their ports are in an initialization mode in which the ports are unable to transmit locally generated DHCP packets. When a network device detects that a neighbor (or “peer”) device has acquired an IP address or has been configured by a network controller, then the port on which the neighbor device is detected can then be transitioned from the initialization mode into a forwarding mode. In the forwarding mode, the port can be used to transmit packets to obtain an IP address. Thus, the network devices are converted from an L2 device to an L3 device in a hierarchical order such that upstream devices are discovered and converted into L3 devices before downstream devices.

Abstract: A method of wireless communication by a base station includes receiving a user equipment (UE) radio capability and a UE machine learning capability. The method also includes determining a neural network function (NNF) based on the UE radio capability. The method includes determining a neural network model. The neural network model includes a model structure and a parameter set, based on the NNF, the UE machine learning capability, and a capability of a network entity. The method also includes configuring the network entity with the neural network model.

Abstract: This disclosure provides systems, methods, and devices for wireless communication that support AI model-based enhancements for RRC IDLE and INACTIVE state operations. In a first aspect, a method of wireless communication includes receiving, by a wireless communication device, artificial intelligence (AI) model configuration information for IDLE/INACTIVE state procedures; retrieving, by the wireless communication device, an AI model for IDLE/INACTIVE state procedures based on the AI model configuration information; and performing, by the wireless communication device, one or more IDLE/INACTIVE state procedures based on the AI model. Other aspects and features are also claimed and described.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Abstract: Various examples are directed to systems and methods for executing an enterprise resource planning solution using a database management system (DBMS). An order-to-cash process executing at the at least one processor accesses an indication of waste material for disposal and generates a waste disposal order, where the waste disposal order comprises a material description field including a description of the waste material, regulatory reporting data describing at least one report of the waste material to be provided to a regulatory agency, and a price field indicating a negative price.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.

Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) may receive control signaling indicating a measurement configuration for minimization of drive test measurement and reporting supporting broadcast receptions within a single-frequency network. The UE may determine, based at least in part on the measurement configuration, a set of measurements for the single-frequency network. The UE may transmit a minimization of drive test report indicating the set of measurements.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.