Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Abstract: Embodiments provide methods and systems for providing a loyalty program to a merchant. The loyalty program is created using a loyalty program ruleset. The loyalty program ruleset is accessed using a merchant identifier of a merchant and a unique identifier data of a user. The unique identifier is captured from a payment card of the user by a merchant terminal. Further, a payment amount for a payment transaction of the user is mapped into a loyalty point data using the loyalty program ruleset. After the mapping, a redeemability of total redeemable loyalty points from the loyalty point data is determined. After determining the redeemability, a redeemable loyalty points is deducted from the total redeemable loyalty points based on a pre-defined number of loyalty points. The payment amount is adjusted based on the redeemable loyalty points. The loyalty program ruleset is also used for determining loyalty reward points for the user.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Abstract: Embodiments provide methods, and server systems for enhancing checkout experience of an e-commerce transaction. A method includes receiving, by a server system associated with a payment network, a pre-authentication request signal for a prospective e-commerce transaction for a payment card of user. The pre-authentication request signal includes a time data for an expected transaction time, a transaction amount data, a payment card data and at least one transaction identifier data. The method includes electronically facilitating a pre-authentication of the prospective e-commerce transaction based at least on performing a multi-factor pre-authentication. Upon successful pre-authentication, the method includes storing a pre-authenticated transaction data. The method includes sending a notification signal of successful pre-authentication to a user device.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Abstract: Fifth Generation (5G) Millimeter Wave (mmWave) cellular networks are expected to serve a large set of throughput intensive, ultra-reliable, and ultra-low latency applications. To meet these stringent requirements, while minimizing the network cost, the 3rd Generation Partnership Project has proposed a new transport architecture, where certain functional blocks can be placed closer to the network edge. In this architecture, however, blockages and shadowing in 5G mmWave cellular networks may lead to frequent handovers (HOs) causing significant performance degradation. To meet the ultra-reliable and low-latency requirements of applications and services in an environment with frequent HOs, a Fast Inter-Base Station Ring (FIBR) architecture is described, in which base stations that are in close proximity are grouped together, interconnected by a bidirectional counter-rotating buffer insertion ring network.

Abstract: Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric).

Abstract: An authorization control network includes an attribute control server and an authorization server. The attribute control server is configured to receive from a communications device a credential and a modification request that includes an account identifier, determine a cardholder attribute from the credential, determine an account attribute associated with the account identifier in a card profile database, determine that the cardholder attribute matches the account attribute, and transmit the modification request to the authorization server.

Abstract: The present disclosure generally relates to offline payment transfer. A first electronic device monitors its connectivity to a wide area network and determines it is in the offline mode if it is disconnected from the wide area network. The first electronic device then activates a first offline wallet stored on the first electronic device. The first electronic device establishes a local area network connection with a second electronic device also in the offline mode, the second electronic device having a second offline wallet stored thereon. Payment data is communicated between the first and second electronic devices via the local area network connection. The payment data comprises a payment amount for transfer between the first and second offline wallets. The first and second electronic devices update the first and second offline wallets in response to said transfer of the payment amount.

Abstract: Methods and systems for patching an instance of a composite executing in a runtime environment are provided. A method can include at a computer system comprising a processor and a memory executing, by an application server, one or more instances of a composite, and enabling a patch to be applied to the one or more instances of the composite without stopping execution of the one or more instances in the application server, wherein the patch comprises one or more changes to be made to the composite.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Abstract: An adder uses with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are the same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals to the majority gates can be analog, digital, or a combination of them, which are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate.

Abstract: The disclosure relates in some aspects to forbidden area procedures and connection release management for a user terminal (UT). Forbidden area-related procedures include, for example, using a special paging area code (PAC) in conjunction with a forbidden area, defining a location reporting threshold for a UT based on the proximity of the UT to a forbidden area, or using a default paging area code if a service restriction for a UT has ended. Connection release management includes, for example, a UT sending a request to cause the release of a Radio Connection that the UT no longer needs, or a UT sending a Location Indication (e.g., including a flag requesting release of a connection) to release the connection used for location reporting when a UT is done sending the location information and is going to go back to idle mode.

Abstract: Vector art object deformation techniques applied to digital images by vector art rendering system of a computing device are described. The vector art rendering system is configured to deform vector art objects associated with anchor points within a digital image based solely on the movement of the anchor points. Moreover, the vector art rendering system is also configured to adjust anchor points associated with vector art objects within a digital image based solely on the movement of the vector art objects. Techniques are also described that facilitate the automatic association of path segment and vector art objects to anchor points that possess multiple preexisting vector art object associations.

Abstract: Aspects described herein provide designs to reduce the probability of persistent PF/PO conflicts of different subscriptions for a multi-SIM/USIM UE. A base station may be configured to determine a first conflict avoidance PO based on one or more modified parameters associated with the first conflict avoidance PO. The base station may be further configured to transmit a first paging message in the first conflict avoidance PO in a first DRX cycle. A UE may be configured to receive the one or more modified parameters in SIB. The UE may be configured to determine the first conflict avoidance PO based on the one or more modified parameters. The UE may be further configured to receive the first paging message in the first conflict avoidance PO in the first DRX cycle.

Abstract: This disclosure provides systems, methods and apparatus, and computer programs encoded on computer storage media, for managing paging monitoring by a wireless device. In one aspect, the wireless device may receive a serving cell signal from a cell. The wireless device may determine a delay time based on the serving cell signal. The wireless device may monitor for the paging signal during the determined delay time. The wireless device may stop the monitoring for the paging signal upon or after expiration of the determined delay time. In some aspects, the wireless device may receive an indication of multiple paging signal monitoring occasions from the cell, which may include an indication of a number of synchronization signal blocks (SSBs) to be transmitted from the cell and a number of physical downlink control channel (PDCCH) monitoring occasions per SSB in a paging occasion.

Abstract: A method, apparatus, and computer program product are disclosed for facilitating two-way email communication in manner that obfuscates sender and recipient email addresses. The method includes receiving a correspondence request indication; assigning a first transaction address to a sender and a second transaction address to a recipient; receiving a message from the sender; associating the message from the sender with the first transaction address; and causing a transmission of the message from the sender to the recipient using the first transaction address. A corresponding apparatus and computer program product are also provided.

Abstract: This disclosure relates method and system for protecting a computing device from a malware. In one embodiment, the method may include determining a digital trust certificate of a set of computing instructions to be executed by the computing device. The set of computing instructions may form a part of a boot process of the computing device, and may be a firmware, a boot loader, a kernel, a system driver, a start-up file, or an antimalware. The method may further include establishing a chain of trust by validating the digital trust certificate with the computing device. The digital trust certificate may be pre-registered with a local database, accessible by the computing device, by communicating with a centralized certificate authority and policy server. Upon a positive establishment of the chain of trust, the method may further include allowing an execution of the set of computing instructions by the computing device.

Abstract: The disclosure provides a system for production of reactive intermediates from lignocellulosic biomass. The reactive intermediates can be used as platform chemicals for biological conversions or can be further catalytically upgraded to be used as “drop in” reagents for fuels. The disclosure provides methods and compositions useful for processing biomass to biofuels and intermediates.

Abstract: The present application provides monitoring and managing usage of one or more network-connected devices over a network. The network-connected devices may include devices connected to the Internet of Things (IoT). Some aspects provide systems, methods and computing devices for: receiving usage and rate data associated with network-connected device(s); determining device expenditure data based on the usage and rate data; obtaining allocation information pertaining to a time period; updating information associated with one or more data files with the device expenditure data; comparing the updated information to the allocation information; and determining whether an allocation indicated by the allocation information for the time period is feasible.