Abstract: A structure is disclosed. The structure can include a logic chip, a first conductor, and a plurality of memory dies. The logic chip can be configured to access the plurality of memory dies. Each of the plurality of memory dies can be electrically connected to the logic chip at least through the first conductor. Each of the plurality of memory dies can include a top major surface, a bottom major surface that is parallel to the top major surface, and a minor surface non-parallel to the top major surface and the bottom major surface. Each of the plurality of memory dies can be bonded to the logic chip through the minor surface, where the minor surface comprises artifacts indicative of at least a singulation process applied on a memory die.

Abstract: A bonded structure is disclosed. The bonded structure can include a carrier. The bonded structure can include a first die having a first communications circuitry to format a communication signal according to a first communication protocol and to transmit the communication signal. The bonded structure can also include a protocol switch die having circuitry to receive the communications signal and to convert the communication signal from the first communication protocol to a second communication protocol, wherein the second communication protocol is different from the first communication protocol. The protocol switch die can transmit the communication signal according to the second communication protocol. The bonded structure can also include a second die having a second communications circuitry to receive the communication signal formatted in the second communication protocol.

Abstract: A bonded structure can include a carrier including a first conductive contact and a second conductive contact, a first singulated element including a third conductive contact directly bonded to the first conductive contact without an adhesive, and a second singulated element including a fourth conductive contact directly bonded to the second conductive contact without an adhesive, wherein the first and second conductive contacts are spaced apart by a contact spacing of no more than 250 microns.

Abstract: In some implementations, a method of manufacturing a cooling apparatus includes forming an integrated cooling assembly by attaching a cold plate to a backside of a first die. A first side of the cold plate is spaced apart from the first die to define a channel volume having an inlet portion and an outlet portion that are closed at a second side of the cold plate opposite to the first side. The method further includes attaching the integrated cooling assembly to an interposer, wherein a plurality of second dies is disposed on the interposer, and subsequent to attaching the integrated cooling assembly to the interposer, opening the inlet portion and the outlet portion of the channel volume.

Abstract: Microelectronic devices having stacked electromagnetic coils are disclosed. In one example, a microelectronic device can include a first semiconductor element and a second semiconductor element disposed on the first semiconductor element. The microelectronic device can also include an electromagnetic coil. A first portion of the electromagnetic coil and a second portion of the electromagnetic coil may be spaced apart by the first semiconductor element. A first conductive via extending through the first semiconductor element may connect the first and second portions of the electromagnetic coil. Methods for forming such microelectronic devices are also disclosed.

Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer.

Abstract: Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.

Abstract: A structure is disclosed. The structure can include a first processor core, first one or more wiring layers, second one or more wiring layers, and a first cache chiplet. The first one or more wiring layers can be disposed vertically below the first processor core, with wires of the first one or more wiring layers having a first average wire width. The second one or more wiring layers can be disposed vertically below the first one or more wiring layers, with wires of the second one or more wiring layers having a second average wire width that is larger than the first average wire width. The first cache chiplet can be disposed vertically below the first one or more wiring layers and at least partially embedded within the second one or more wiring layer. The first cache chiplet can be hybrid bonded to the first one or more wiring layers.

Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

Abstract: Methods are disclosed herein for fluid cooling semiconductor devices. A method comprises forming a thermal exchanger on the semiconductor device by etching cavities in the semiconductor device, depositing a thermally conductive layer in the cavities, and forming, from the thermally conductive layer, the thermal exchanger comprising (i) thermal vias disposed in the cavities and (ii) an upper portion of the thermally conductive layer to form protrusions above the first side. The method further comprises coupling a housing to the thermal exchanger to form a fluid chamber having a chamber volume disposed between the thermal exchanger and the housing, where the upper portion of the thermal exchanger is exposed to and faces the chamber volume.

Abstract: Embodiments herein provide for device packages with embedded cooling assemblies. A device package comprises a package substrate comprising a support surface, a device mounted on the support surface, a cold plate body comprising a first side adjacent to the device and a opposite second side, a manifold attached to the second side, and a package cover disposed over the manifold. The cold plate body and the manifold define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold.

Abstract: Embodiments herein provide for an integrated thermal control assembly comprising: a semiconductor device; a cold plate stacked vertically adjacent to the semiconductor device; and a heater device disposed adjacent to the semiconductor device and the cold plate.

Abstract: An integrated cooling assembly comprises a semiconductor device and a device stack disposed in a side-by-side arrangement, an opening adaptor, and a cold plate. The cold plate is attached between the opening adaptor and both the semiconductor device and the device stack. The cold plate comprises a first opening and a second opening spaced apart by a first distance and in fluid communication with a coolant channel, at least a portion of a first side is spaced apart from the semiconductor device and the device stack to define the coolant channel. Sidewalls and a divider of the opening adaptor extend downwardly to a second side of the cold plate. The inlet and outlet openings of the opening adaptor are spaced apart by a second distance different from the first distance.

Abstract: An element that is configured to bond to another element is disclosed. A first element that can include a first plurality of contact pads on a first surface. The first plurality of contact pads includes a first contact pad and a second contact pad that are spaced apart from one another. The first and second contact pads are electrically connected to one another for redundancy. The first element can be prepared for direct bonding. The first element can be bonded to a second element to form a bonded structure. The second element has a second plurality of contact pads on a second surface. At least one of the second plurality of contact pads is bonded and electrically connected to at least one of the first plurality of contact pads.

Abstract: An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.

Abstract: A bonded structure is disclosed. The bonded structure can include a first device layer comprising a reconstituted element having a first die at least partially embedded in an encapsulant. The bonded structure can further include a second device layer comprising a second die bonded to the reconstituted element along a first bonding interface. The bonded structure can also include a first signal test trace positioned between the reconstituted element and the second die. The first signal test trace can be in electrical communication with at least one of the first die and the second die and can extend outwardly from the first bonding interface. The first signal test trace can be positioned such that during singulation of the bonded structure, a portion of the first signal test trace is removed along a cutting path and a remaining portion extends to an edge of the singulated bonded structure.

Abstract: An interposer assembly may include a substrate, a dielectric layer on a first surface of the substrate, and a first bridge die embedded in the dielectric layer. The substrate can include a plurality of first vias. The first bridge die can include a plurality of bridge die routing layers.

Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.

Abstract: A bonded structure with a package substrate comprising an inorganic, insulating first bonding layer and first conductive features at a surface thereof and an electronic component comprising an inorganic, insulating second bonding layer and second conductive features at a surface thereof wherein the first bonding layer and the second bonding layer are directly bonded to one another, and the first and second conductive features are directly bonded to one another.

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.