Abstract: A display comprises a plurality of LEDs on a substrate. Each pixel of the display comprises one or more LEDs of the plurality of LEDs and a transparent region of the display. The transparent region transmits light external to the display through the display.

Abstract: A system automatically prioritizes and resumes disconnected customer interactions. The system includes a processor to perform operations that include: receiving a list of disconnected customer interactions, including their metadata; using a prioritization module and the metadata, assigning a priority score to each disconnected interaction; with a queuing module and the respective priority scores, with an agent assignment module, arranging the disconnected interactions in a priority order; assigning an available agent to each disconnected interaction in the priority order; selecting a channel for each disconnected interaction in the priority order, based on a channel recommendation module and the metadata; and re-connecting a disconnected customer with the respective agent via the respective channel for each respective disconnected customer interaction in the priority order.

Abstract: A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.

Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

Abstract: Direct-bonded lamination for improved image clarity in optical devices is provided. An example process planarizes and plasma-activates optical surfaces to be laminated together, then forms direct bonds between the two surfaces without an adhesive or adhesive layer. This process provides improved optics with higher image brightness, less light scattering, better resolution, and higher image fidelity. The direct bonds also provide a refractory interface tolerant of much higher temperatures than conventional optical adhesives. The example process can be used to produce many types of improved optical components, such as improved laminated lenses, mirrors, beam splitters, collimators, prism systems, optical conduits, and mirrored waveguides for smartglasses and head-up displays (HUDs), which provide better image quality and elimination of the dark visual lines that are apparent to a human viewer when conventional adhesives are used in conventional lamination.

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Abstract: Conductive features of a device including quantum dots of a first substrate are bonded to conductive features of a second substrate. A quantum dot layer is formed on the first substrate having conductive features in a dielectric layer. Hybrid bonding of the first substrate to the second substrate is performed without use of an intervening adhesive to connect the first conductive features and the second conductive features.

Abstract: An image sensor using quantum dots is formed that improves collection of photogenerated carrier using a conductive matrix, a semiconductive matrix, a matrix comprising conductive particles and quantum dots in a transparent non-conductive material, conductive structures, and/or porous conductive structures. Hybrid bonding of the image sensor to an image processor device is performed without use of an intervening adhesive to connect the image sensor to the image processor device.

Abstract: A method of forming a stacked image sensor comprises providing a first substrate and a second substrate. The first substrate comprises a first matrix comprising first quantum dots, a first dielectric layer adjacent to the first matrix, and first bond pads disposed in the first dielectric layer. The second substrate comprises a second matrix comprising second quantum dots, a second dielectric layer adjacent to the second matrix, and second bond pads disposed in the second dielectric layer. The method includes hybrid bonding the first substrate to the second substrate without use of an intervening adhesive to form the stacked image sensor, where the hybrid bonding connects the first bond pads to the second bond pads.

Abstract: Disclosed is a microelectronic structure including a first element and a through substrate via (TSV) structure. The first element includes a bulk portion having a front side and a back side opposite the front side. The TSV structure is disposed in an opening extending at least partially through the bulk portion from the front side to the back side. The TSV structure includes a conductive tip portion and a second conductive via portion. The second conductive via portion is disposed between the front side and the conductive tip portion. The conductive tip portion contains a different conductive material than the second conductive via portion.

Abstract: Conductive features of a device including quantum dots of a first substrate are bonded to conductive features of a second substrate. A quantum dot layer is formed on the first substrate having conductive features in a dielectric layer. Hybrid bonding of the first substrate to the second substrate is performed without use of an intervening adhesive to connect the first conductive features and the second conductive features.

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer.

Abstract: A device package comprising an integrated cooling assembly. The integrated cooling assembly comprising a semiconductor device and a manifold attached to the semiconductor device. The manifold comprises a top portion, a spacer extending downwardly from the top portion to a backside of the semiconductor device, and a vibrational membrane disposed between portions of the manifold. The top portion, the spacer, and the backside of the semiconductor device collectively define a coolant chamber volume therebetween.

Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

Abstract: A semiconductor element is provided with a micro-structured metal oxide layer over a conductive feature at a hybrid bonding surface. The micro-structured metal oxide layer comprises fine metal oxide grains, such as nanograins. The grains can be formed over the conductive feature by oxidizing a metal comprised in the conductive feature, or by providing a metal oxide over the conductive feature. When directly bonded to another element, the micro-structured metal oxide layer can form strong bonds at the bonding interface at substantially reduced annealing temperature.

Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

Abstract: A device including a first integrated device die and a semiconductor device. The first integrated device die can include a die insulating layer and a die conductive feature at least partially embedded in the die insulating layer. The semiconductor device can include a first insulating layer on the first surface, a device conductive feature at least partially embedded in the first insulating layer, and a first heavily doped semiconductor material electrically connected to the device conductive feature. The die conductive feature can be connected to power or ground through at least the first heavily doped semiconductor material.

Abstract: A bonded optical device is disclosed. The bonded optical device can include a first optical element, a second optical element, and an optical pathway. The first optical element has a first array of optical emitters configured to emit light of a first color. The first optical element is bonded to at least one processor element, the at least one processor element including active circuitry configured to control operation of the first optical element. The second optical element has a second array of optical emitters configured to emit light of a second color different from the first color. The second optical element is bonded to the at least one processor element. The optical pathway is optically coupled with the first and second optical elements. The optical pathway is configured to transmit a superposition of light from the first and second optical emitters to an optical output to be viewed by users.