Abstract: An element that is configured to bond to another element is disclosed. A first element that can include a first plurality of contact pads on a first surface. The first plurality of contact pads includes a first contact pad and a second contact pad that are spaced apart from one another. The first and second contact pads are electrically connected to one another for redundancy. The first element can be prepared for direct bonding. The first element can be bonded to a second element to form a bonded structure. The second element has a second plurality of contact pads on a second surface. At least one of the second plurality of contact pads is bonded and electrically connected to at least one of the first plurality of contact pads.

Abstract: An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.

Abstract: A bonded structure is disclosed. The bonded structure can include a first device layer comprising a reconstituted element having a first die at least partially embedded in an encapsulant. The bonded structure can further include a second device layer comprising a second die bonded to the reconstituted element along a first bonding interface. The bonded structure can also include a first signal test trace positioned between the reconstituted element and the second die. The first signal test trace can be in electrical communication with at least one of the first die and the second die and can extend outwardly from the first bonding interface. The first signal test trace can be positioned such that during singulation of the bonded structure, a portion of the first signal test trace is removed along a cutting path and a remaining portion extends to an edge of the singulated bonded structure.

Abstract: An interposer assembly may include a substrate, a dielectric layer on a first surface of the substrate, and a first bridge die embedded in the dielectric layer. The substrate can include a plurality of first vias. The first bridge die can include a plurality of bridge die routing layers.

Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.

Abstract: A bonded structure with a package substrate comprising an inorganic, insulating first bonding layer and first conductive features at a surface thereof and an electronic component comprising an inorganic, insulating second bonding layer and second conductive features at a surface thereof wherein the first bonding layer and the second bonding layer are directly bonded to one another, and the first and second conductive features are directly bonded to one another.

Abstract: An element includes a substrate and a surface layer on the substrate. The surface layer includes at least one first region comprising an optically transparent and electrically insulative first material and at least one second region at least partially embedded in the at least one first region. The at least one second region comprises an optically transparent and electrically conductive second material.

Abstract: An element that is configured to bond to another element is disclosed. A first element that can include a first plurality of contact pads on a first surface. The first plurality of contact pads includes a first contact pad and a second contact pad that are spaced apart from one another. The first and second contact pads are electrically connected to one another for redundancy. The first element can be prepared for direct bonding. The first element can be bonded to a second element to form a bonded structure. The second element has a second plurality of contact pads on a second surface. At least one of the second plurality of contact pads is bonded and electrically connected to at least one of the first plurality of contact pads.

Abstract: An integrated device package is disclosed. The integrated device package can include an antenna structure and an integrated device die electrically coupled to the antenna structure. The antenna structure can be formed with a system board or separated from the system board. When the antenna structure is formed with the system board, the integrated device package can include a redistribution layer having conductive routing traces such that the integrated device die is disposed between the system board and the redistribution layer, and the integrated device die is electrically coupled to the antenna structure at least partially through the redistribution layer. When the antenna structure is separated from the system board, the integrated device die can be positioned between the antenna structure and the system board, and the integrated device die can be electrically coupled to the antenna structure at least partially through the system board.

Abstract: Embodiments herein provide for an integrated thermal control assembly comprising: a semiconductor device; a cold plate stacked vertically adjacent to the semiconductor device; and a heater device disposed adjacent to the semiconductor device and the cold plate.

Abstract: A display device comprises a plurality of first LEDs disposed in a first passivation layer. Each first LED has a first electrode disposed on the respective first LED and a second electrode that is electrically coupled to a control device. A contact of at least one second LED is directly bonded to the first electrode of at least one first LED. The second LED and the first electrode of the at least one first LED are disposed in a second passivation layer. An electrode of the second LED is electrically connected to a same control device that the second electrode of the at least one first LED is connected to.

Abstract: Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

Abstract: A structure is disclosed. The structure can include a first plurality of integrated device dies, an interconnect device, and an optical unit. The interconnect device can be electrically connected to the first plurality of integrated device dies. The optical unit can be disposed vertically above the interconnect device. The optical unit can be optically connected to an optical interconnect. The first plurality of integrated device dies can communicate with a second plurality of integrated device dies at least through the interconnect device, the optical unit, and the optical interconnect.

Abstract: An electronic component including a first device die hybrid bonded to a carrier, an encapsulant encapsulating side surfaces of the first device die and a cover element disposed over directly bonded to a top surface of the first device die.

Abstract: An element includes a substrate and a surface layer on the substrate. The surface layer includes at least one first region comprising an optically transparent and electrically insulative first material and at least one second region at least partially embedded in the at least one first region. The at least one second region comprises an optically transparent and electrically conductive second material.

Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

Abstract: Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.

Abstract: Direct-bonded optoelectronic interconnects for high-density integrated photonics are provided. A combined electrical and optical interconnect enables direct-bonding of fully-processed optoelectronic dies or wafers to wafers with optoelectronic driver circuitry. The photonic devices may be III-V semiconductor devices. Direct-bonding to silicon or silicon-on-insulator (SOI) wafers enables the integration of photonics with high-density CMOS and other microelectronics packages. Each bonding surface has an optical window to be coupled by direct-bonding. Coplanar electrical contacts lie to the outside, or may circumscribe the respective optical windows and are also direct-bonded across the interface using metal-to-metal direct-bonding, without interfering with the optical windows. Direct hybrid bonding can accomplish both optical and electrical bonding in one overall operation, to mass-produce mLED video displays.

Abstract: A bonded optical device is disclosed. The bonded optical device can include a first optical element, a second optical element, and an optical pathway. The first optical element has a first array of optical emitters configured to emit light of a first color. The first optical element is bonded to at least one processor element, the at least one processor element including active circuitry configured to control operation of the first optical element. The second optical element has a second array of optical emitters configured to emit light of a second color different from the first color. The second optical element is bonded to the at least one processor element. The optical pathway is optically coupled with the first and second optical elements. The optical pathway is configured to transmit a superposition of light from the first and second optical emitters to an optical output to be viewed by users.

Abstract: A power delivery substrate may include a doped semiconductor including ground blocks, power blocks parallel to and coplanar with the ground blocks, and an insulator between the ground and power blocks. A first insulator layer can be disposed over the doped semiconductor and include first trenches and second trenches. The first and second trenches can be crossing with the ground and power blocks. First conductive traces may be included in the first trenches and in electrical contact with the ground blocks. Second conductive traces may be included in the second trenches and in electrical contact with the power blocks. A second insulator layer can be disposed over the first and the second conductive traces, and bonding pads can be embedded in the second insulator layer. The bonding pads can be electrically connected to the first and the second conductive traces.