Patents by Inventor Rajesh Katkar

Rajesh Katkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253294
    Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.
    Type: Application
    Filed: December 27, 2024
    Publication date: August 7, 2025
    Inventors: Guilian Gao, Bongsub Lee, Gaius Gillman Fountain, JR., Cyprian Emeka Uzoh, Belgacem Haba, Laura Wills Mirkarimi, Rajesh Katkar
  • Patent number: 12381119
    Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: August 5, 2025
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Rajesh Katkar, Liang Wang, Cyprian Emeka Uzoh, Shaowu Huang, Guilian Gao, Ilyas Mohammed
  • Publication number: 20250226290
    Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.
    Type: Application
    Filed: November 20, 2024
    Publication date: July 10, 2025
    Inventors: Belgacem Haba, Thomas Workman, Cyprian Emeka Uzoh, Guilian Gao, Rajesh Katkar
  • Publication number: 20250221128
    Abstract: A display device comprises a first substrate and a second substrate. The first substrate includes a plurality of singulated control devices embedded in a first dielectric layer. The second substrate includes a plurality of singulated LEDs embedded in a second dielectric layer. The second substrate is directly bonded to the first substrate without an intervening adhesive.
    Type: Application
    Filed: October 29, 2024
    Publication date: July 3, 2025
    Inventors: Rajesh Katkar, Belgacem Haba, Cyprian Emeka Uzoh, Guilian Gao, Thomas Workman
  • Publication number: 20250210459
    Abstract: A device package comprising an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening, and an outlet opening. The top portion, the sidewalls, and the backside of the semiconductor device collectively define a coolant chamber volume therebetween. The inlet opening and the outlet opening are disposed in the top portion and are in fluid communication with the coolant chamber volume. The inlet opening is disposed above a hotspot region of the semiconductor device.
    Type: Application
    Filed: August 1, 2024
    Publication date: June 26, 2025
    Inventors: Belgacem Haba, Rajesh Katkar, Ron Zhang, Thomas Workman, Gaius Gillman Fountain, JR.
  • Publication number: 20250212554
    Abstract: A method of transferring a plurality of individual elements including providing a plurality of singulated elements on a stretchable tape, stretching the stretchable tape to increase separation between the singulated elements and forming a reconstituted wafer with at least one of the plurality of elements.
    Type: Application
    Filed: June 17, 2024
    Publication date: June 26, 2025
    Inventors: Rajesh Katkar, Belgacem Haba, Cyprian Emeka Uzoh, Guilian Gao, Thomas Workman
  • Publication number: 20250201739
    Abstract: A method of bonding substrates comprises depositing a fluorine-doped dielectric layer on a first substrate, exposing the fluorine-doped dielectric layer to a hydrogen-containing plasma, and directly bonding the fluorine-doped dielectric layer to a surface of a second substrate without the use of an intervening adhesive.
    Type: Application
    Filed: December 15, 2023
    Publication date: June 19, 2025
    Inventors: Cyprian Emeka Uzoh, Belgacem Haba, Rajesh Katkar, Oliver Zhao
  • Patent number: 12322650
    Abstract: Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.
    Type: Grant
    Filed: September 3, 2024
    Date of Patent: June 3, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh
  • Patent number: 12322667
    Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: June 3, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Rajesh Katkar, Liang Wang, Cyprian Emeka Uzoh, Shaowu Huang, Guilian Gao, Ilyas Mohammed
  • Patent number: 12324268
    Abstract: Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.
    Type: Grant
    Filed: February 2, 2024
    Date of Patent: June 3, 2025
    Assignee: Adeia Semiconductor Technologies LLC
    Inventor: Rajesh Katkar
  • Patent number: 12300634
    Abstract: A bonded structure with protective semiconductor elements including a semiconductor element with active circuitry and a protective element including an obstructive layer and/or a protective circuitry layer. The obstructive layer is configured to inhibit external access to at least a portion of the active circuitry. The protective circuitry layer is configured to detect or disrupt external access to the protective element and/or the active circuitry of the semiconductor element. The semiconductor element and the protective element are directly bonded without an adhesive along a bonding interface.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 13, 2025
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Belgacem Haba, Laura Wills Mirkarimi, Christopher Aubuchon, Rajesh Katkar
  • Publication number: 20250151502
    Abstract: A display comprises a plurality of LEDs on a substrate. Each pixel of the display comprises one or more LEDs of the plurality of LEDs and a transparent region of the display. The transparent region transmits light external to the display through the display.
    Type: Application
    Filed: November 6, 2024
    Publication date: May 8, 2025
    Inventors: Belgacem Haba, Rajesh Katkar
  • Patent number: 12288771
    Abstract: A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.
    Type: Grant
    Filed: November 27, 2023
    Date of Patent: April 29, 2025
    Assignee: Adeia Semiconductor Technologies LLC
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Rajesh Katkar, Pearl Po-Yee Cheng
  • Patent number: 12289428
    Abstract: A system automatically prioritizes and resumes disconnected customer interactions. The system includes a processor to perform operations that include: receiving a list of disconnected customer interactions, including their metadata; using a prioritization module and the metadata, assigning a priority score to each disconnected interaction; with a queuing module and the respective priority scores, with an agent assignment module, arranging the disconnected interactions in a priority order; assigning an available agent to each disconnected interaction in the priority order; selecting a channel for each disconnected interaction in the priority order, based on a channel recommendation module and the metadata; and re-connecting a disconnected customer with the respective agent via the respective channel for each respective disconnected customer interaction in the priority order.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: April 29, 2025
    Assignee: NICE LTD.
    Inventors: Bhupendra Pandey, Dhanendra Singh, Rajesh Katkar, Salil Dhawan
  • Patent number: 12283572
    Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.
    Type: Grant
    Filed: October 13, 2023
    Date of Patent: April 22, 2025
    Assignee: Adeia Semiconductor Technologies LLC
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Rajesh Katkar
  • Publication number: 20250125248
    Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.
    Type: Application
    Filed: July 24, 2024
    Publication date: April 17, 2025
    Inventors: Belgacem Haba, Ilyas Mohammed, Rajesh Katkar, Gabriel Z. Guevara, Javier A. DeLaCruz, Shaowu Huang, Laura Wills Mirkarimi
  • Patent number: 12270970
    Abstract: Direct-bonded lamination for improved image clarity in optical devices is provided. An example process planarizes and plasma-activates optical surfaces to be laminated together, then forms direct bonds between the two surfaces without an adhesive or adhesive layer. This process provides improved optics with higher image brightness, less light scattering, better resolution, and higher image fidelity. The direct bonds also provide a refractory interface tolerant of much higher temperatures than conventional optical adhesives. The example process can be used to produce many types of improved optical components, such as improved laminated lenses, mirrors, beam splitters, collimators, prism systems, optical conduits, and mirrored waveguides for smartglasses and head-up displays (HUDs), which provide better image quality and elimination of the dark visual lines that are apparent to a human viewer when conventional adhesives are used in conventional lamination.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: April 8, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Belgacem Haba, Rajesh Katkar, Ilyas Mohammed
  • Patent number: 12272677
    Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
    Type: Grant
    Filed: February 27, 2024
    Date of Patent: April 8, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Belgacem Haba, Gabriel Z. Guevara, Joy Watanabe
  • Publication number: 20250113641
    Abstract: A method of forming a stacked image sensor comprises providing a first substrate and a second substrate. The first substrate comprises a first matrix comprising first quantum dots, a first dielectric layer adjacent to the first matrix, and first bond pads disposed in the first dielectric layer. The second substrate comprises a second matrix comprising second quantum dots, a second dielectric layer adjacent to the second matrix, and second bond pads disposed in the second dielectric layer. The method includes hybrid bonding the first substrate to the second substrate without use of an intervening adhesive to form the stacked image sensor, where the hybrid bonding connects the first bond pads to the second bond pads.
    Type: Application
    Filed: September 25, 2024
    Publication date: April 3, 2025
    Inventors: Rajesh Katkar, Belgacem Haba, Cyprian Emeka Uzoh, Oliver Zhao
  • Publication number: 20250113646
    Abstract: Conductive features of a device including quantum dots of a first substrate are bonded to conductive features of a second substrate. A quantum dot layer is formed on the first substrate having conductive features in a dielectric layer. Hybrid bonding of the first substrate to the second substrate is performed without use of an intervening adhesive to connect the first conductive features and the second conductive features.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 3, 2025
    Inventors: Rajesh Katkar, Belgacem Haba, Cyprian Emeka Uzoh