Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry and a first bonding layer. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over the active circuitry and a second bonding layer on the obstructive material. The second bonding layer can be directly bonded to the first bonding layer without an adhesive. The obstructive material can be configured to obstruct external access to the active circuitry.

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

Abstract: A bonded optical device is disclosed. The bonded optical device can include a first optical element, a second optical element, and an optical pathway. The first optical element has a first array of optical emitters configured to emit light of a first color. The first optical element is bonded to at least one processor element, the at least one processor element including active circuitry configured to control operation of the first optical element. The second optical element has a second array of optical emitters configured to emit light of a second color different from the first color. The second optical element is bonded to the at least one processor element. The optical pathway is optically coupled with the first and second optical elements. The optical pathway is configured to transmit a superposition of light from the first and second optical emitters to an optical output to be viewed by users.

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.

Abstract: A bonded structure can include a carrier including a first conductive contact and a second conductive contact, a first singulated element including a third conductive contact directly bonded to the first conductive contact without an adhesive, and a second singulated element including a fourth conductive contact directly bonded to the second conductive contact without an adhesive, wherein the first and second conductive contacts are spaced apart by a contact spacing of no more than 250 microns.

Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

Abstract: An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

Abstract: An integrated device package is disclosed. The integrated device package can include a carrier, and a cap bonded to the carrier. The carrier and the cap at least partially define a cavity that is configured to receive a coolant. The integrated device package can include an inorganic material layer disposed at least on a portion of the carrier. At least a portion of the inorganic material layer is exposed to the cavity and configured to contact the coolant. The cap can be directly bonded to the carrier without an intervening adhesive. The integrated device package can include an integrated device die that is disposed in the cavity and bonded to the carrier. The integrated device die can be directly bonded to the carrier without an intervening adhesive.

Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer.

Abstract: A bonded structure with a package substrate comprising an inorganic, insulating first bonding layer and first conductive features at a surface thereof and an electronic component comprising an inorganic, insulating second bonding layer and second conductive features at a surface thereof wherein the first bonding layer and the second bonding layer are directly bonded to one another, and the first and second conductive features are directly bonded to one another.

Abstract: Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

Abstract: A bonded structure comprising a first semiconductor element, a second semiconductor element spaced apart from the first semiconductor element by a gap, and an interconnect assembly comprising an insulating substrate with conductive traces, the insulating substrate including a first section directly bonded to the first semiconductor element, a second section directly bonded to the second semiconductor element, and a flexible section disposed between the first and second sections, the flexible section at least partially bridging the gap.

Abstract: In some aspects, the disclosed technology provides microelectronic devices which can effectively dissipate heat and manage hot spot. In some embodiments, a disclosed microelectronic device may include a substrate having a thickness in a first direction and at least one thermoelectric unit disposed in or on the substrate. The thermoelectric unit may be configured to transfer heat along a second lateral direction orthogonal to the first direction.

Abstract: In some aspects, the disclosed technology provides microelectronic devices which can effectively dissipate heat and methods of forming the disclosed microelectronic devices. In some embodiments, a disclosed device may include a first integrated device die. The disclosed device may further include a thermoelectric element bonded to the first integrated device die. The disclosed device may further include a heat sink disposed over at least the thermoelectric element. The thermoelectric element may be configured to transfer heat from the first integrated device die to the heat sink. The thermoelectric element directly may be bonded to the first integrated device die without an adhesive.

Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation.

Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

Abstract: An element that is configured to bond to another element to define a bonded structure is disclosed. The element can include a dielectric bonding layer having a cavity that extends at least partially through a thickness of the dielectric bonding layer from a surface of the dielectric bonding layer. The element can also include a conductive feature that is at least partially disposed in the cavity. The conductive feature has a contact surface. The element can include a diffusion barrier layer between the conductive feature and a portion of the dielectric bonding layer. The barrier layer includes a barrier metal. The barrier metal of the diffusion barrier layer has an oxidation propensity that is greater than an oxidation propensity of the conductive feature.

Abstract: An integrated device package is disclosed. The integrated device package can include an antenna structure and an integrated device die electrically coupled to the antenna structure. The antenna structure can be formed with a system board or separated from the system board. When the antenna structure is formed with the system board, the integrated device package can include a redistribution layer having conductive routing traces such that the integrated device die is disposed between the system board and the redistribution layer, and the integrated device die is electrically coupled to the antenna structure at least partially through one or more of the conductive routing traces of the redistribution layer.