Patents by Inventor Rajesh S

Rajesh S has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090197594
    Abstract: A system and method for providing call mobility for a dual-mode phone between a cellular network and a home wireless network for a dual-mode phone having a cellular identity and a home identity, wherein the home identity is active when the dual-mode phone is in communication with the home wireless network. The system comprises a residential gateway to connect the home wireless network to a public network, and a VoIP service provider in communication with a mobile switching center on the cellular network and the public network. After placing or receiving a call, the dual-mode phone sends a signal to the residential gateway to initiate the movement of the call between the cellular network and the home wireless network while the call is ongoing.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 6, 2009
    Applicant: GENERAL INSTRUMENT CORPORATION
    Inventors: Suresh Kumar Chintada, Rajashekaran E. Ethiraju, Rupak K. Maiti, Rajesh S. Pazhyannur, Satyanarayana T
  • Publication number: 20090154347
    Abstract: De-jittering a transport stream, at least some transport packets of the transport stream carrying audio-video data and at least some of the transport packets of the transport stream containing Program Clock References (PCRs). A data buffer receives the transport packets and stores the transport packets. Pacing counter clock circuitry produces a pacing counter clock and adjusts the pacing counter clock based upon a pacing counter clock adjust signal. Pacing control circuitry produces the pacing counter clock adjust signal based upon receipt of the transport packets. PCR packet pacing circuitry receives the pacing counter clock, based upon the packing counter clock, retrieves transport packets from the data buffer, and transmits the retrieved transport packets as an output transport stream. The pacing counter clock adjust signal may be based upon data buffer fullness or based upon an estimated program clock generated from the PCRs.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 18, 2009
    Applicant: Broadcom Corporation
    Inventors: Rajesh S. Mamidwar, Wade Wan, John Jordan
  • Patent number: 7523152
    Abstract: A method for an extended precision integer divide algorithm includes separating an L-bit integer dividend into two equal width integer format portions, a first portion including lower M bits of the integer dividend and a second portion including upper M bits of the integer dividend, where M is equal to ½ L. An N-bit wide integer divisor is converted from an integer format into a floating point format divisor. The first integer portion is converted into a floating point format and divided by the floating point format divisor to obtain a first floating point quotient, which is converted into a first integer format quotient. The second integer portion is converted into a floating point format and divided by the floating point format divisor to obtain a second floating point quotient which is also converted to a second integer format quotient. Then first and second integer format quotients are summed together to generate a third integer format quotient.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: April 21, 2009
    Assignee: Intel Corporation
    Inventors: Patrice L. Roussel, Rajesh S. Parthasarathy
  • Publication number: 20090097514
    Abstract: A femtosecond laser based laser processing system having a femtosecond laser, frequency conversion optics, beam manipulation optics, target motion control, processing chamber, diagnostic systems and system control modules. The femtosecond laser based laser processing system allows for the utilization of the unique heat control in micromachining, and the system has greater output beam stability, continuously variable repetition rate and unique temporal beam shaping capabilities.
    Type: Application
    Filed: December 19, 2008
    Publication date: April 16, 2009
    Applicant: IMRA America, Inc.
    Inventors: Lawrence SHAH, James M. Bovatsek, Alan Y. Arai, Tadashi Yamamoto, Rajesh S. Patel, Donald J. Harter
  • Patent number: 7509393
    Abstract: A method, a system, an apparatus, and a computer program product are presented for a fragment caching methodology. After a message is received at a computing device, a fragment in the message body is cached. Cache ID rules from an origin server accompany a fragment to describe a method for forming a unique cache ID for the fragment such that dynamic content can be cached away from an origin server. A cache ID may be based on a URI and/or query parameters and/or cookies that are associated with a fragment. After user authentication, a cookie containing the user's role may be used in subsequent requests for role-specific fragments and in the cache identifier for role-specific fragments, thereby allowing requests from other users for role-specific fragments to be resolved in the cache when the users have the same role because these users would also have the same cookie.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: March 24, 2009
    Assignee: International Business Machines Corporation
    Inventors: Rajesh S. Agarwalla, James R. H. Challenger, George P. Copeland, Arun K. Iyengar, Mark H. Linehan, Subbarao Meduri
  • Patent number: 7506121
    Abstract: Embodiments of apparatuses, methods, and systems for guests to access memory mapped devices are disclosed. In one embodiment, an apparatus includes evaluation logic and exit logic. The evaluation logic is to determine, in response to an attempt of a guest to access a device using a memory address mapped to the device and based on an access type, whether the access is allowed. The exit logic is to transfer control to a host if the evaluation logic determines that the access is not allowed.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: March 17, 2009
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Andrew V. Anderson, Steven M. Bennett, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Rajesh S. Parthasarathy, Sebastian Schoenberg
  • Publication number: 20090070551
    Abstract: In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.
    Type: Application
    Filed: September 6, 2007
    Publication date: March 12, 2009
    Inventors: Shivnandan D. Kaushik, Keshavan K. Tiruvallur, James B. Grossland, Sridhar Muthrasanallur, Rajesh S. Parthasarathy, Luke P. Hood
  • Publication number: 20090070511
    Abstract: In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.
    Type: Application
    Filed: September 6, 2007
    Publication date: March 12, 2009
    Inventors: Shivnandan D. Kaushik, Keshavan K. Tiruvallur, James B. Crossland, Sridhar Muthrasanallur, Rajesh S. Parthasarathy, Luke P. Hood
  • Publication number: 20090050140
    Abstract: A nozzle comprising a thin, flexible substantially planar polymeric film having a plurality of pores with structures allowing for generation of an aerosol at reduced extrusion pressure is disclosed. The pores can comprise at least two sections, or steps, in which the thickness of the membrane is reduced in stepwise fashion, or the pores can be tapered. Nozzles formed comprising pores having such structures permit aerosol generation at lower extrusion pressures, thereby allowing for decreased weight of aerosolization devices, increased efficiency, increased portability and increased battery life. The pore structures also allow for the use of thicker, more easily processed polymeric films in manufacturing while having a thinner, more efficient aerosolization area. The use of decreased extrusion pressures also results in increased uniformity in aerosol generation and improved reliability of other components.
    Type: Application
    Filed: October 15, 2007
    Publication date: February 26, 2009
    Inventors: Rajesh S. PATEL, Sudarsan Srinivasan
  • Patent number: 7491909
    Abstract: A method for laser machining of material using a burst comprised of laser pulses. The method tailors the pulse width, pulse separation duration, wavelength and polarization of the multiple laser pulses included in a burst to maximize the positive effect of thermal and physical changes achieved by previous pulses that have impinged upon the machined material.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: February 17, 2009
    Assignee: IMRA America, Inc.
    Inventors: Tadashi Yamamoto, Donald J. Harter, Rajesh S. Patel, Alan Y. Arai
  • Patent number: 7486705
    Abstract: A femtosecond laser based laser processing system having a femtosecond laser, frequency conversion optics, beam manipulation optics, target motion control, processing chamber, diagnostic systems and system control modules. The femtosecond laser based laser processing system allows for the utilization of the unique heat control in micromachining, and the system has greater output beam stability, continuously variable repetition rate and unique temporal beam shaping capabilities.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: February 3, 2009
    Assignee: IMRA America, Inc.
    Inventors: Lawrence Shah, James M Bovatsek, Alan Y Arai, Tadashi Yamamoto, Rajesh S. Patel, Donald J. Harter
  • Publication number: 20080308534
    Abstract: In a laser annealing system for workpieces such as semiconductor wafers, a pyrometer wavelength response band is established within a narrow window lying between the laser emission band and a fluorescence emission band from the optical components of the laser system, the pyrometer response band lying in a wavelength region at which the optical absorber layer on the workpiece has an optical absorption coefficient as great as or greater than the underlying workpiece. A multi-layer razor-edge interference filter having a 5-8 nm wavelength cut-off edge transition provides the cut-off of the laser emission at the bottom end of the pyrometer response band.
    Type: Application
    Filed: June 18, 2007
    Publication date: December 18, 2008
    Inventors: Jiping Li, Bruce E. Adams, Timothy N. Thomas, Aaron Muir Hunter, Abhilash J. Mayur, Rajesh S. Ramanujam
  • Patent number: 7467381
    Abstract: The present disclosure relates to the resource management of virtual machine(s) using hardware address mapping, and, more specifically, to facilitate direct access to devices from virtual machines, utilizing control of hardware address translation facilities.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Rajesh S. Madukkarumukumana, Gilbert Neiger, Ioannis Schoinas
  • Publication number: 20080288583
    Abstract: A method, system, and computer program product, by which portions of the session information that page-content is dependent upon are “pushed” to the client from the origin server in a way such that auxiliary servers, e.g. other application servers and edge-servers, have access to the session information and fragment dependancy data to generate auxiliary-server cache-IDs for the custom pages. This enables distribution of the load away from the origin server, allowing better application distribution and scalability through more effective caching.
    Type: Application
    Filed: February 27, 2008
    Publication date: November 20, 2008
    Applicant: International Business Machines Corporation
    Inventors: Rajesh S. Agarwalla, Madhu Chetuparambil, Steven D. Ims, Brian K. Martin, Thomas F. McElroy, Subbarao Meduri, Daniel C. Shupp, Brad B. Topol
  • Patent number: 7451197
    Abstract: Provided are a method, system, and article of manufacture. A network communication request is received at an offload application, wherein the offload application interfaces with a first network stack implemented in an operating system and a second network stack implemented in a hardware device. A determination is made if the network communication request can be processed by the second network stack. If the network communication request can be processed by the second network stack, then the network communication request is offloaded for processing to the hardware device.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: November 11, 2008
    Assignee: Intel Corporation
    Inventors: Arlin R. Davis, Rajesh S. Madukkarumukumana, Stan C. Smith
  • Patent number: 7440928
    Abstract: Apparatus and method for determining a likely cause or the likelihood of the occurrence of a cause of one or more effects, in which training data relating to previously identified relationships between one or more causes and one or more effects is used to learn the cause and effect relationship. A number of primary and secondary reference points are chosen in the input space created by belief values representing the strength of effect. A function representing the cause and effects relationship and a weight value is associated with each reference point. Weight values associated with primary reference points are considered as independent variables (primary weight values) and other weight values, which are associated with secondary reference points (secondary weight values), depend on one or more primary weight values. Belief value in the occurrence of likely causes of one or more given effects can be determined using this method or apparatus.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: October 21, 2008
    Assignee: MetaCause Solutions Ltd.
    Inventors: Rajesh S. Ransing, Meghana R. Ransing, Roland W. Lewis
  • Publication number: 20080243999
    Abstract: A method and a communication system having an Application Ensemble Service server is provided that manage an application ensemble having multiple applications running on one or more user terminals. The communication system allows a user to collectively transfer the ensemble from a source terminal or terminals to a target terminal or terminals, for example, from voice and data terminals to other voice and data terminals or to a single user terminal. The communication system further allows the user to selectively transfer applications of the ensemble, such as transferring only the voice session from the voice terminal to another voice or voice/data terminal, and to copy an ensemble, or a portion of an ensemble, from a source terminal to a target terminal, wherein the ensemble or portion of the ensemble is not removed from the source terminal. The communication system further allows a user to suspend and resume an application ensemble.
    Type: Application
    Filed: March 12, 2008
    Publication date: October 2, 2008
    Applicant: MOTOROLA, INC.
    Inventors: Rajesh S. Pazhyannur, Gaurav S. Gupta
  • Publication number: 20080235461
    Abstract: A bridge includes a memory to establish a transaction table and write combining windows. Each write combining window is associated with a cache line and is subdivided into subwindows; and each of the subwindows is associated with a partial cache line. The bridge includes a controller to determine whether an incoming partial write transaction conflicts with a transaction stored in the transaction table. If a conflict occurs, the controller uses the write combining windows to combine the partial write transaction with another partial write transaction if one of the partial write combining windows is available. The controller issues a retry signal to a processor originating the partial write transaction if none of the partial write combining windows are available.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Inventors: Sin Tan, Kai Cheng, Rajesh S. Pamujula, Sivakumar Radhakrishnan, Dhananjay Joshi
  • Patent number: 7412535
    Abstract: A method, a system, an apparatus, and a computer program product are presented for a fragment caching methodology. After a message is received at a computing device that contains a cache management unit, a fragment in the message body of the message is cached. Subsequent requests for the fragment at the cache management unit result in a cache hit. A FRAGMENTLINK tag is used to specify the location in a fragment for an included or linked fragment which is to be inserted into the fragment during fragment or page assembly or page rendering. If a FRAGMENTLINK tag is present within the message body of a message, then the FRAGMENT message header for the message may indicate the presence of the FRAGMENTLINK tag with a directive for the FRAGMENT message header, e.g., using a “contains-fragment” directive.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: August 12, 2008
    Assignee: International Business Machines Corporation
    Inventors: Rajesh S. Agarwalla, James R. H. Challenger, George P. Copeland, Arun K. Iyengar, Mark H. Linehan
  • Patent number: 7406583
    Abstract: An autonomic computing environment is provided by sequestering one of a plurality of processor resources, partitioning a memory, and hiding an input/output (I/O) device. One processor resource is sequestered such that the sequestered processor resource is not exposed to the remaining processor resources as a processor resource. A memory region is partitioned to provide a service processing portion such that the sequestered processor resource has access to all of the memory region and the remaining processor resources have access to at least a portion of the memory region but do not have access to the service processing portion. A first I/O device is hidden such that the sequestered processor resource has access to the first I/O device and the remaining processor resources do not have access to the first I/O device.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventors: Ulhas Warrier, Rajesh S. Madukkarumukumana