Abstract: Method for compiling program instructions to reduce instruction cache misses and instruction cache pollution. The program is analyzed for instructions which result in a non-sequential transfer of control in the program. The presence of branch instructions and program loops are identified and analyzed. The instructions are placed in lines, and the lines are placed in a sequence to minimize potential misses.

Abstract: A Multiple Instruction Stream Multiple Data Stream (MIMD) parallel processing apparatus and compiling method for effectuating collective branching of execution by the processors includes specialized branch and fuzzy barrier units which operate with respect to special instructions scheduled in unshaded regions of the instruction streams of the processors involved in a collective branch. A special compare instruction is scheduled in a first unshaded region of only one of the processors while a special jump instruction is scheduled in the next unshaded region of the instruction stream of the other involved processors. By the special jump instruction, the other processors use the special compare result which is simultaneously passed to each of them by the branch unit for determining the execution branch. The barrier unit provides fuzzy barrier synchronization assuring that the correct compare result is used in this determination.

Abstract: A circuit for use on an integrated circuit chip for detecting the operative connection of a crystal used to control an on-chip crystal controlled oscillator, which generates a cyclical clock signal, by detecting the presence or absence, respectively, of the cyclical clock signal and for providing an output control signal in response thereto to an on-chip terminal pad control circuit which automatically enables an on-chip terminal pad to be utilized as a clock signal output terminal pad if the cyclical clock signal presence is detected or as a clock signal input terminal pad otherwise. Also, a method of automatically switching the function of a terminal pad on an integrated circuit chip to function as a clock signal output terminal pad or as a clock signal input terminal pad in accordance with detecting the existence or non-existence of a cyclical clock signal generated on-chip.