Abstract: Interconnect-dominated large register files are reduced in chip area and delay time. A register file in a processor having a number of execution units is divided into multiple copies. Different groups of execution units can read from and write to their own copy of the file registers by a set of local read and write ports. All of the register-file copies are synchronized by writing data from the execution units to remote write ports in at least some registers in other copies of the register file. Each copy can be divided into local and global registers. While all copies of the global registers continue to be written by the remote write ports, the local registers can be written only by a local cluster of execution units. Alternatively or additionally, all of the execution units can write to their local register-file copy, but only some of the units can write the global registers in all copies of the register file.

Abstract: A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.

Abstract: A system for selling personal information through a trusted third party. An owner of the personal information provides policy governing the sale of the owner's personal information and authorizes information sources to provide the personal information to the trusted third party. The trusted third party provides for validation of the personal information and sells it to requesters in accordance with the policy, and provides payment or credit to the owner as compensation for the sale.

Abstract: A system and method for controlling the scheduling of threads in a multi-thread processor system. The multi-thread processor system has a multi-thread processor, a main memory, a cache memory, and a thread scheduler. Information is sent from the cache memory to the thread scheduler for determining which thread the processor is going to execute. The thread scheduler calculates or maintains a figure of merit for each thread executing on the processor. The figure of merit determines which thread to switch to when the current or previous thread has a long latency. The figure of merit define the execution environment as measured by the performance of the cache memory. The figure of merit can be the owner of a particular thread, the number of data lines accessed by a particular thread which resides in the cache, the number of times a particular thread has hit in the cache over a specified time interval, the thread that installed the data or the thread that was used most recently.

Abstract: A computer system with mechanisms for providing hint instructions to a processor without altering object code instruction sequences. A computer system according to the present teachings includes elements for generating a hint instruction in response to a set of object code to be executed by the processor and for inserting a break instruction into the object code such that the break instruction causes the processor to obtain and execute the hint instruction. The present techniques for providing hint instructions to a processor may be used to adapt object code to a micro-architecture of the processor.

Abstract: A method for look-ahead load pre-fetching that reduces the effects of instruction stalls caused by high latency instructions. Look-ahead load pre-fetching is accomplished by searching an instruction stream for load memory instructions while the instruction stream is stalled waiting for completion of a previous instruction in the instruction stream. A pre-fetch operation is issued for each load memory instruction found. The pre-fetch operations cause data for the corresponding load memory instructions to be copied to a cache, thereby avoiding long latencies in the subsequent execution of the load memory instructions.

Abstract: A programmable aerosol generator forms a volatilized liquid by supplying a material in liquid form to a flow passage and heating the flow passage, such that the material volatilizes and expands out of an outlet of the channel. The volatilized material, if desired, mixes with ambient air such that volatilized material condenses to form the aerosol. An apparatus and method for generating such a volatilized liquid, as well as the control and methods of heating, are disclosed as an analytical tool useful for experimental use, a tool useful for production of commercial products or an inhaler device.

Abstract: A system for performing image-based diagnosis of a machine includes a database containing a plurality of historical images taken from a plurality of machines, a diagnostic unit configured to diagnose a new artifact image from the machine and to communicate historical and non-historical images or data associated with the system to a remote facility. The plurality of historical images include a plurality of ideal images generated from the plurality of machines using all possible machine settings and a plurality of artifact images generated from the plurality of machines, each of the artifact images having known faults associated therewith and a corresponding corrective action for repairing the faults. The diagnostic unit includes a diagnostic image processor and a diagnostic fault isolator.

Abstract: A software system with self-describing attribute vocabularies that enhance the capability of service providers to advertise their resources and that facilitate the addition of new types of attributes and resources to the system. Each self-describing attribute vocabulary is characterized by a corresponding set of attribute properties and a corresponding set of:matching rules that are adapted to the corresponding attribute properties. The software system includes a matching engine that enables a service provider of a resource to describe the resource to the software system in terms of any one or more of the self-describing attribute vocabularies.

Abstract: A software system that provides access control to resources and that disassociates access rights to resources from references to resources to prevent the formation of large and unwieldy access control lists and to enable advanced decentralized security controls. The software system includes a repository that holds a resource descriptor for each resource including lock/permission pairs. Access to particular resources or groups of resources is provided by providing users with the appropriate keys. The keys are themselves are resources with resource descriptors in the repository. Access rights for users may be revoked by deleting keys from the repository. The software system also provides visibility fields for compartmentalizing access to resources. In addition, the software system provides authorizers that maintain audit trails when critical resource such as keys are passed among users and that enable advanced security control when passing resources among users.

Abstract: The method of prefetching data into cache to minimize CPU stall time uses a rough predictor to make rough predictions about what cache lines will be needed next by the CPU. The address difference generator uses the rough prediction and the actual cache miss address to determine the address difference. The prefetch engine builds a data structure to represent address differences and weights them according to the accumulated stall time produced by the cache misses given that the corresponding address is not prefetched.

Abstract: A method is provided for generating an aerosol. The method includes preparing a solution formed of a first component in a liquid component such that after volatilization of the liquid component by passing the solution through a flow passage while heating the solution, an aerosol is formed having a predetermined particle size distribution of the first component, wherein the solution is prepared such that the amount of the first component therein is sufficient to achieve the predetermined particle size distribution of the first component. The method also includes passing the solution through the flow passage while heating the solution to a temperature sufficient to volatilize the liquid component, wherein the flow passage comprises an outlet through which the first component and the volatilized liquid component flow, and wherein an aerosol is formed.

Abstract: A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time.

Abstract: A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache memory which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.

Abstract: An analysis system and method provide for quantitatively evaluating image quality characteristics of an ultrasound imaging machine that evaluates at least one image representation of a standard phantom acquired by the image machine. The machine under test by comparing acquired parameters with prestored values, and returning a determined set of image quality indices, along with a single index representing an arithmetic combination of all other image quality indices, which indicate the accuracy of the test image relative to a “gold standard” that has been pre-established for the model of imaging machine under investigation. The system, which includes a computer-programmed set of instructions and data, optionally includes at least one standard phantom.

Abstract: Computer apparatus includes an execution unit for executing a sequence of instructions which may include a speculative load instruction, a memory for storing data required by the instructions for execution, a low latency data cache for holding data accessed in the memory in response to the instructions, a low latency data buffer for holding speculative data accessed in the memory in response to the speculative load instruction, and a controller. The controller loads the speculative data from the memory into the data buffer in response to the speculative load instruction when the speculative data is not present in the data cache or the data buffer, and loads the speculative data from the data buffer into the execution unit. The speculative data may be loaded from the data buffer into the execution unit when the speculative load instruction is executed or when the speculative load instruction is committed.

Abstract: A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time.

Abstract: A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache memory which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.

Abstract: A method for detecting thread switch conditions provides first and second scoreboard bits for each register in a register file. The first scoreboard bit associated with a register is set when a load is generated to return data to the register. The second scoreboard bit is set if the load misses in a selected processor cache. Register read instructions are monitored, and a thread switch condition is indicated when a register read instruction to the register is detected while its first and second scoreboard bits are set.

Abstract: A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time.