Abstract: A software infrastructure for providing an open digital services marketplace including a naming manager that enables a requesting task to refer to a desired resource using a name which is local to the requesting task and a router that forwards the request to an appropriate handler for the desired resource and that enables at least one additional task to be invoked in response to the request. The infrastructure includes a permission manager that compares a set of access rights of the requesting task to the desired resource to a set of permissions associated with the desired resource such that the access rights are kept separately from the reference to the desired resource. The desired resource, the requesting task, the additional task, and a set of additional components used to handle the request are each modeled as a resource defined by a corresponding set of meta-data which includes a set of attributes and a reference to a grammar for interpreting the attributes.

Abstract: A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache memory which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.

Abstract: Locally-adaptive, sub-voxel registration of two volumetric data sets is performed by generating match points and then, using the match points, generating a locally-adaptive image-to-warp transformation. Generation of the match points is accelerated by generating a volume hierarchy and then identifying a set of 3D points in the first volume for designation as interesting points. Interesting points in the first volume are then matched with their corresponding points in the second volume. After performing match point generation, points on a cubic grid in the first volume are matched to the corresponding match points in the second volume by resampling the match points on the cubic grid in the first volume. After a grid of match points has been identified, the displacement (dx, dy, dz) that should be added to each cubic grid point in the first volume to identify the coordinates of the corresponding point in the second volume is determined.

Abstract: The present invention discloses a system and method for performing image-based diagnosis. In this invention, historical artifact images and corresponding actions for repairing the artifacts are acquired and stored in a database. The database of historical artifact images and corresponding actions is used to diagnose an incoming artifact image having an unknown fault.

Abstract: A method and apparatus for optimizing code using resource based partial elimination techniques is disclosed. At least one location is identified in the code wherein the at least one location has available resources. One of the plurality of instructions is moved to the at least one location according to partial elimination techniques.

Abstract: A method and apparatus for optimizing execution of code is disclosed. The code is executed to generate path profiling information. At least one location is identified for relocating at least one of the plurality of instructions in the code, where the at least one location is enabled by one of predication and speculation. A cost and a benefit are calculated for relocating the at least one of the plurality of instructions to the at least one location, the cost and the benefit based on the path profiling information. The at least one of the plurality of instructions is moved to the at least one location when the benefit exceeds the cost, and one of predication and speculation is performed on the one of the plurality of instructions. The code is then reexecuted.

Abstract: A microprocessor is provided which includes a power control register for controlling the rate of execution and therefore the power consumption of individual functional units. The power control register includes a plurality of fields corresponding to the functional units for storing values that control the power consumption of each. The power control register fields can be set by software which has the much greater ability to look out into the future to determine whether the functional units will be required. The functional units are responsive to the corresponding power control register field to adjust their rate of execution responsive to the value stored therein. The rate of execution can be controlled in a number of different ways: dividing down the clock; removing power to the functional unit; disabling the sensor and/or buffer driver of one or more of the ports in a multi-ported RAM; removing data from the functional unit; and changing the data bus width responsive to the control register field.

Abstract: A memory management system is described which divides each virtual page into two or more sectors. Each of these sectors can then be individually loaded into memory in order to reduce bandwidth consumed loading virtual pages into a physical memory. A TLB for this system includes a plurality of TLB entries. Each TLB entry includes a variable physical page number (PPN FIELD) and a variable presence field. Each bit of the presence field indicates whether a corresponding sector is present in physical memory. The TLB entry also includes a page size field, which indicates the size of the corresponding virtual page. This size field also indirectly controls the number of sectors within that page and, thus, the number of presence bits required. As the page size grows the number of bits required to store the physical page number reduces. These unused bits are then consumed by additional presence bits so that all the bits in the TLB entry are used for all page sizes and number of sectors.

Abstract: A method for executing instructions out-of-order to improve performance of a processor includes compiling the instructions of a program into separate queues along with encoded dependencies between instructions in the different queues. The processor then issues instructions from each of these queues independently, except that it enforces the encoded dependencies among instructions from different queues. If an instruction is dependent on instructions in other queues, the processor waits to issue it until the instructions on which it depends are issued. The processor includes a stall unit, comprised of a number of instruction counters for each queue, that enforces the dependencies between instructions in different queues.

Abstract: An instruction cache which separates storage cells for instruction data from storage cells for sequence control is disclosed. Instructions are decoded prior to being stored to the instruction cache which serves a primary cache, while prior hierarchical levels of memory store instructions in an encoded form. Because the instructions have a variable-length, the instruction cache includes a next address determination circuit to determine the next instruction address. The invention is advantageous because the separation of storage cells enables a next instruction address to be generated during a fetch stage for a current instruction, thereby avoiding the need for an otherwise necessary additional decoding stage. A bypass mechanism useful for any cache following a cache miss is also disclosed.

Abstract: The inventive system and method allows for software control of hardware drral of exceptions in speculative operations, and comprises three components. The first component is processor stored information which reflects the code generation strategy of applications and is used by hardware and the operating system to control exception deferral. The second component is processor stored information set by the operating system to specify to hardware which type of faults should be automatically deferred. The third component is further processor stored information which indicates to the hardware to defer certain exception causing aspects of the speculative operation, while performing other non excepting aspects of the speculative operation. The stored information is set after the operating system exception handler has unsuccessfully attempted fault resolution.

Abstract: A method and related control logic for performing in line recovery from deferred exceptions generated by speculative operations. The control logic includes a re-execution register to mark operands of operations that should be re-executed in a special recovery mode. When the processor detects a deferred exception, it branches to the operation that generated the exception and enters the special in-line recovery mode. The processor executes operations non-speculatively in the recovery mode, and marks the result registers of these operations with re-execution flags. The processor then knows whether to re-execute an operation by checking for re-execution flags associated with the operands of an in-line operation. The processor exits recovery mode when it returns to the point where it detected the deferred exception. The re-execution register enables the processor to recover from deferred exceptions using the program code only, without any additional fix-up code or recovery code.

Abstract: A locally-adaptive method for obtaining sub-pixel registration of mask and opacified digital X-ray images includes the steps of match point generation, locally-adaptive image-to-image warp generation, and log subtraction, for generating a DSA image. Specifically, in match point generation, a set of two-dimensional points in the mask image and their corresponding points in the opacified image are derived. After match point generation, locally-adaptive image-to-image warp generation is performed using the image-to-image match points; that is, a transformation function is generated that maps the matched points in the mask image to their corresponding points in the opacified image. The generated transformation is then applied to the mask image data and the logarithm of the pixel value in the transformed (i.e., warped) mask image is subtracted from the logarithm of the corresponding pixel value in the opacified image.

Abstract: A barrier is used to synchronize parallel processors. The barrier is "fuzzy", i.e. it includes several instructions in each instruction stream. None of the processors performing related tasks can execute an instruction after its respective fuzzy barrier until the others have finished the instruction immediately preceding their respective fuzzy barriers. Processors therefore spend less time waiting for each other. A state machine is used to keep track of synchronization states during the synchronization process.

Abstract: A circuit and method for clipping input integers to a specified range comprising the steps of providing a mask wherein a bit is set for each out-of-range bit and not set for in-range bits and applying the mask to input integers so that any integers outside of the range is clipped to the quantity in the range closest to the integer, thereby producing output integers within a range specified by the mask. Other systems and methods are disclosed.

Abstract: A barrier is used to synchronize parallel processors. The barrier is "fuzzy", i.e. it includes several instructions in each instruction stream. None of the processors performing related tasks can execute an instruction after its respective fuzzy barrier until the others have finished the instruction immediately preceding their respective fuzzy barriers. Processors therefore spend less time waiting for each other. A state machine is used to keep track of synchronization states during the synchronization process.

Abstract: A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.

Abstract: A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, and which also specifies a target address of the branch. A block of target instructions, starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of limited memory bandwidth.

Abstract: To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.

Abstract: A system of accurately positioning a manufactured part in a calibrated position, involves positioning the part on a structure. Adjusting the part on the structure such that points on the surface of the part known to be accurate and drilling notches in the part at known locations. Distances from the surface of the part to the structure in `x` and `z` directions, and a rotation angle .theta. are measured. The part is then placed in a fixture having a nest plate with pins which hold the part by the notches thereby defining an axis through the part. A `z` stop is adjusted to the measured `z` distance which stops rotation of the part about the axis between the pins. An `x` stop is set to the measured x distance which stops translation of the part along the axis between the pins. The nest plate is pivotally attached to the base plate allowing the nest plate to rotate with respect to the base plate the rotational angle .theta.. This results in calibrated positioning of the part allowing maximum access to the part.