Abstract: A method and related control logic for performing in line recovery from deferred exceptions generated by speculative operations. The control logic includes a re-execution register to mark operands of operations that should be re-executed in a special recovery mode. When the processor detects a deferred exception, it branches to the operation that generated the exception and enters the special in-line recovery mode. The processor executes operations non-speculatively in the recovery mode, and marks the result registers of these operations with re-execution flags. The processor then knows whether to re-execute an operation by checking for re-execution flags associated with the operands of an in-line operation. The processor exits recovery mode when it returns to the point where it detected the deferred exception. The re-execution register enables the processor to recover from deferred exceptions using the program code only, without any additional fix-up code or recovery code.

Abstract: A locally-adaptive method for obtaining sub-pixel registration of mask and opacified digital X-ray images includes the steps of match point generation, locally-adaptive image-to-image warp generation, and log subtraction, for generating a DSA image. Specifically, in match point generation, a set of two-dimensional points in the mask image and their corresponding points in the opacified image are derived. After match point generation, locally-adaptive image-to-image warp generation is performed using the image-to-image match points; that is, a transformation function is generated that maps the matched points in the mask image to their corresponding points in the opacified image. The generated transformation is then applied to the mask image data and the logarithm of the pixel value in the transformed (i.e., warped) mask image is subtracted from the logarithm of the corresponding pixel value in the opacified image.

Abstract: A barrier is used to synchronize parallel processors. The barrier is "fuzzy", i.e. it includes several instructions in each instruction stream. None of the processors performing related tasks can execute an instruction after its respective fuzzy barrier until the others have finished the instruction immediately preceding their respective fuzzy barriers. Processors therefore spend less time waiting for each other. A state machine is used to keep track of synchronization states during the synchronization process.

Abstract: A circuit and method for clipping input integers to a specified range comprising the steps of providing a mask wherein a bit is set for each out-of-range bit and not set for in-range bits and applying the mask to input integers so that any integers outside of the range is clipped to the quantity in the range closest to the integer, thereby producing output integers within a range specified by the mask. Other systems and methods are disclosed.

Abstract: A barrier is used to synchronize parallel processors. The barrier is "fuzzy", i.e. it includes several instructions in each instruction stream. None of the processors performing related tasks can execute an instruction after its respective fuzzy barrier until the others have finished the instruction immediately preceding their respective fuzzy barriers. Processors therefore spend less time waiting for each other. A state machine is used to keep track of synchronization states during the synchronization process.

Abstract: A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.

Abstract: A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, and which also specifies a target address of the branch. A block of target instructions, starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of limited memory bandwidth.

Abstract: To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.

Abstract: A system of accurately positioning a manufactured part in a calibrated position, involves positioning the part on a structure. Adjusting the part on the structure such that points on the surface of the part known to be accurate and drilling notches in the part at known locations. Distances from the surface of the part to the structure in `x` and `z` directions, and a rotation angle .theta. are measured. The part is then placed in a fixture having a nest plate with pins which hold the part by the notches thereby defining an axis through the part. A `z` stop is adjusted to the measured `z` distance which stops rotation of the part about the axis between the pins. An `x` stop is set to the measured x distance which stops translation of the part along the axis between the pins. The nest plate is pivotally attached to the base plate allowing the nest plate to rotate with respect to the base plate the rotational angle .theta.. This results in calibrated positioning of the part allowing maximum access to the part.

Abstract: A method and system are disclosed which allow a computer program to execute properly in object code compatible processing systems which have latencies different from those with which the program was created or compiled. This resulting compatibility of the computer program is achieved because the invention protects the precedence of operations within the computer program using latency assumptions which were used when creating the computer program. When the computer program is created, latency assumption information is efficiently provided within the computer program. Thereafter, when the computer program is executed, it is able to advise the processing system of the latency assumptions with which it was created. Various ways are described in which the processing system can utilize the latency assumptions when executing the computer program so as to ensure compatibility.

Abstract: A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.

Abstract: The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.

Abstract: A high-speed address translation look-aside buffer (TLB) for translating an explicit address, comprised of an index, a TLB index, and an offset, into a physical address. The TLB cooperates with a space register file having a plurality of space registers, each space register having an indirect address for a corresponding index value. The TLB includes a memory organized as N TLB entries, each entry having an entry space tag, a virtual tag, a valid bit, and a physical page number. A comparator is coupled to each entry which compares only the TLB index to the virtual tag. Each TLB entry further includes a matching bit memory for pre-storing the results of comparing the contents of the entry space tag with the contents (indirect address) of the space registers. The contents of the matching bit memories are then selected during the memory translation process to indicate the result of the prior comparison.

Abstract: An improved data processing system for executing branch instructions which has lower latency times and which only rarely requires the instruction pipeline to be flushed is disclosed. The data processing system utilizes a register file to hold the information needed to execute a branch instruction. The information is loaded into the register file in advance of the branch instruction. This allows the system to prepare more than one branch instruction at any given time. The present invention may be used to cause the cache line containing the target address of the branch instruction to be loaded soon as the target address is available for the branch instruction. Since the outcome of the branch instruction is almost always known when the branch instruction enters the instruction pipeline, the instruction pipeline only rarely needs to be flushed.

Abstract: A conditional substitution instruction is provided in an instruction set of a computer system to correct exceptions occurring during run-time. The conditional substitution instruction can be executed concurrently in a pipelined computer system with a potentially excepting instruction, or simultaneously in a wide computer system. The conditional substitution instruction substitutes a default value for the result of the potentially excepting instruction if the potentially excepting instruction produces one or more specified exceptions.

Abstract: A communications protocol using group ordered message processing is disclosed. According to the protocol, a sending application groups messages together. The messages within the groups are then processed by a receiving application in the order received, but the groups themselves are processed in the order sent. More specifically, the invention pertains to a method for receiving messages at a processor node from another processor node via a plurality of communication paths. The method includes the steps of: receiving a message having a required number of messages value, comparing the required number of messages value with a number of processed messages, and determining whether the message is ready to be processed based on the result of the comparison. The invention can also be implemented as an apparatus. As an apparatus, the invention pertains to a processing node for a communication system which transmits messages between processing nodes interconnected by multiple communication paths.

Abstract: In a digital computer, a circular queue of registers in a register file are allocated as temporary local storage for procedures rather than using the known caller/callee save convention in order to minimize main memory references. A called procedure dynamically allocates local registers as needed without regard to registers used by the caller of the procedure or by any callee of the procedure, whereby register allocation is not restricted by any predetermined window size. Local registers, including parameter passing registers, are allocated in the called procedure, rather than a priori at compile time, by adjusting register stack pointer values. Only the number of registers actually required by the procedure need by allocated. Optionally, rotating registers may be allocated among the local registers. Stack pointer values are stored in one of the parameter passing registers when a procedure is called.

Abstract: A method of reconstructing selected features of a part manufactured according to a CAD model involves acquiring a set of linear push broom (LPB) projection images of the part acquired at different angles about an axis of rotation passing through the part. Acquiring a set of matrices M.sub.j j=1 . . . N, each of which maps 3D coordinates of the part to screen coordinates of one of the projection images. Reconstruction of 3D structures from the projection images requires identification of screen coordinates of each image which correspond to a point of the structure of the part to be reconstructed. Back projecting these screen coordinates modified by the distortion inherent in the LPB imaging device. This is accomplished by selecting a screen coordinate on a feature desired to be reconstructed. Computing a ray passing through the selected screen coordinate through an imaging center. Using each M matrix to map this ray to a hyperbola on the other images.

Abstract: A method of calibrating a linear pushbroom imaging device used in non-destructive testing of a part manufactured according to a CAD model involves identifying the location of fixed reference points, such as tooling balls in the CAD model. Positioning the part on a fixture having tooling balls fixed relative to each other in the same manner as those in the CAD model. Adjusting the part on the fixture such that points on the surface of the part known to be accurate have the same locations relative to the tooling bails as the CAD part is to the CAD tooling balls. Obtaining several projection images of the part and tooling balls at different angles about an axis of rotation passing through the part. Using the known 3D locations of the center of the CAD tooling balls and the corresponding measured screen locations of the is actual tooling balls, transformation matrices, G, M.sub.

Abstract: An on-board regulated voltage up-convertor for converting a first DC voltage at a first node from an electronic system to a second DC voltage for an integrated device at a second node. The convertor comprises reference generator means for generating a predetermined reference voltage at start-up, voltage regulator means coupled to said first node for regulating said first voltage at a predetermined voltage at a third node, voltage multiplier means coupled to said third node and to said second node for multiplying said predetermined voltage to generate an output voltage substantially equal to said second voltage, feedback means coupled to said second node for feeding said output voltage back to said voltage regulator means to adjust the level of said predetermined voltage at said third node according to how said output voltage is relative to said second voltage.