Abstract: A singled ended current sense amplifier circuit including an input stage having a bitline node, a sense node and a feedback circuit comprising a feedback inverter configured to provide an amplified voltage from the bitline node. The feedback inverter may include first and second NMOS transistors serially connected to a feedback node and first and second PMOS transistors serially connected to the feedback node. The feedback circuit may include a third NMOS transistor having a gate terminal connected to the feedback node and a drain terminal connected to the sense node. The input stage may include a third PMOS transistor operating as a current source to generate a sense current which flows in a current sensing path between the sense node and the bitline node. The input stage may act as a regulator to keep the voltage at the bitline node constant.

Abstract: An improved electronic mixed mode multiplier and accumulate circuit for artificial intelligence and computing system applications that perform vector-vector, vector-matrix and other multiply-accumulate computations. The circuit is provided is a high resolution, high linearity, low area, low power multiply—accumulate (MAC) unit to interface with a memory device for storing computation output results. The MAC unit uses a less number of current carrying elements resulting in much lower integrated circuit area, and provides a tight matching between the current elements thus preserving inherent linearity requirements due to current mode operation. Further the MAC performs current scaling using switches and current division where the current switches occupy minimum size transistors requiring a small area to implement that renders it compatible with MRAM such as a magnetic tunnel junction device.

Abstract: A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

Abstract: A sense amplifier circuit includes a bitline node, a sense node, and a feedback circuit which is connected to the bitline node and to the sense node. The feedback circuit includes a cascode-connected pair of transistors configured to isolate the bitline node from an occurrence of a voltage variation on the sense node.

Abstract: An apparatus includes multiple signal paths for signal transmission, and control circuitry. The multiple signal paths include a first signal path and a second signal path. The first signal path is configured to convert a digital baseband signal to a first radio frequency (RF) signal having a first frequency and a first gain. The second signal path is configured to convert a digital baseband signal to a second RF signal having a second frequency and a second gain, wherein the second gain is less than the first gain. The control circuitry is coupled to the plurality of signal paths and is configured to receive one or more control signals to enable selective activation of at least one signal path of the plurality of signal paths.

Abstract: Transmitters, sensor systems, and methods of transmission include a frequency adjuster coupled to a ring oscillator to reduce latency and power consumption and to receive a signal from the ring oscillator. The frequency adjuster includes logic circuits to adjust the signal to a selected transmission frequency band. A band switch is coupled to the ring oscillator and the frequency adjuster to select logic circuits within the frequency adjuster to determine the selected transmission frequency band from a set of output frequency bands. A first radio front end is coupled to the frequency adjuster to transmit the signal on the selected transmission frequency band.

Abstract: Systems and methods for monitoring current anomaly are described. In an example, a device can measure first current flowing along a first liner between an instrument to an equipment. The device can measure second current flowing along a second line between the equipment to the instrument. The device can compare the measurements of the first current and the second current. The device can identify a presence of current anomaly based on the comparison of the measurements of the first and second currents. The device can, in response to the presence of the current anomaly, disconnect the instrument from the equipment.

Abstract: Transmitters, sensor systems, and methods of transmission include a frequency adjuster coupled to a ring oscillator to reduce latency and power consumption and to receive a signal from the ring oscillator. The frequency adjuster includes logic circuits to adjust the signal to a selected transmission frequency band. A band switch is coupled to the ring oscillator and the frequency adjuster to select logic circuits within the frequency adjuster to determine the selected transmission frequency band from a set of output frequency bands. A first radio front end is coupled to the frequency adjuster to transmit the signal on the selected transmission frequency band.

Abstract: Transmitters and methods of transmitting a polar-modulated signal include a driver to output a polar-modulated signal according to a phase-modulation signal and an amplitude-modulation signal. A voltage regulator is connected to the driver, with the amplitude-modulation signal controlling an input of the voltage regulator and with the amplitude-modulation signal further being combined with an output of the voltage regulator to control an amplitude of the output of the driver to compensate for bandwidth cutoff noise in the voltage regulator.

Abstract: System and methods for implementing a multiply and accumulate (MAC) operation are described. In an example, a device can multiply an input digital signal with an input current to generate a current signal. The device can further divide the current signal into a plurality of currents. The device can further sample the plurality of currents sequentially using the same clock frequency. The device can further combine the plurality of sampled currents to generate an output current signal.

Abstract: An apparatus includes a plurality of signal processing stages configured to convert a digital baseband signal into an analog radio frequency signal for transmission. The signal processing stages are configured to be operatively coupled to a positive supply voltage and a negative supply voltage. At least one signal processing stage of the plurality of signal processing stages is configured to generate an analog voltage signal which comprises a voltage level that is outside of a voltage range defined by the positive supply voltage and the negative supply voltage.

Abstract: A wireless power system includes a phase locked loop (PLL) providing an input signal tuned in frequency, a plurality of dividers coupled to the PLL to divide the frequency of the input signal, a plurality of phase interpolators electrically connected to the plurality of dividers to generate multiple phases based on the input signal, and a plurality of drivers electrically connected to the plurality of phase interpolators to direct a plurality of output signals each having a different frequency to a plurality of sensor clusters, each sensor cluster operating at a different frequency.

Abstract: A quantum processing system includes a first set of control electronics operating at a first temperature. A second set of control electronics is communicatively coupled to the first set of control electronics and operating at a second controlled temperature that is lower than the first temperature. The second set of control electronics includes one or more circuits configured to perform a write and a read operation to one or more qubits. There is a qubit array that includes the one or more qubits and operating at a third controlled temperature that is lower than the second temperature. The qubit array is controlled by the second set of control electronics.

Abstract: A method of validating support circuits of a qubit array includes generating virtual control waveforms from one or more abstracted support circuits of the qubit array. An abstracted pulse sequence is created from the virtual control waveforms. The abstracted pulse sequence is converted into waveforms. The waveforms are sent to individual qubits of the qubit array. Output data from the qubit array is captured in response to the sent waveforms.

Abstract: An apparatus includes multiple signal paths for signal transmission, and control circuitry. The multiple signal paths include a first signal path and a second signal path. The first signal path is configured to convert a digital baseband signal to a first radio frequency (RF) signal having a first frequency and a first gain. The second signal path is configured to convert a digital baseband signal to a second RF signal having a second frequency and a second gain, wherein the second gain is less than the first gain. The control circuitry is coupled to the plurality of signal paths and is configured to receive one or more control signals to enable selective activation of at least one signal path of the plurality of signal paths.

Abstract: A sense amplifier circuit includes a bitline node, a sense node, and a feedback circuit which is connected to the bitline node and to the sense node. The feedback circuit includes a cascode-connected pair of transistors configured to isolate the bitline node from an occurrence of a voltage variation on the sense node.

Abstract: Systems and methods to implement a multiply and accumulate (MAC) unit is described. In an example, a device can include a first current mode digital-to-analog converter (DAC) configured to multiply an input signal with a first current having a first amplitude to generate a first signal. The device can further include a second current mode DAC configured to multiply the input signal with a second current having a second amplitude to generate a second signal. The second amplitude can be less than the first amplitude. The device can further include a mixer configured to multiply the second signal with a clock signal to generate a third signal. The third signal can be combined with the first signal via a current summing node to generate an output signal. The output signal can be outputted to another device.

Abstract: An apparatus which includes a multiphase signal generator circuit. The multiphase signal generator circuit is configured to receive as input a complementary analog signal having a fundamental frequency, and generate a plurality of output complementary analog signals. Each output complementary analog signal comprises the same fundamental frequency as the input complementary analog signal, and wherein each output complementary analog signal comprises a different phase.

Abstract: A method of validating support circuits of a qubit array includes generating virtual control waveforms from one or more abstracted support circuits of the qubit array. An abstracted pulse sequence is created from the virtual control waveforms. The abstracted pulse sequence is converted into waveforms. The waveforms are sent to individual qubits of the qubit array. Output data from the qubit array is captured in response to the sent waveforms.

Abstract: A low power transmitter includes a low frequency feedback loop, a high frequency switching element embedded within the low frequency feedback loop, and a mixer electrically communicating with the low frequency feedback loop and the high frequency switching element. The low frequency feedback loop employs either a voltage mode interface or a current mode interface. The high frequency switching element includes a first transistor, a second transistor, and a pair of inductive elements. Alternatively, the high frequency switching element includes a single transistor and a single inductive element.