Patents by Inventor Rakesh Jain

Rakesh Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor Heterostructure with Stress Management
    Publication number: 20170338371
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Application
    Filed: July 26, 2017
    Publication date: November 23, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Daniel Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Heterostructure including a composite semiconductor layer
    Patent number: 9818826
    Abstract: A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: November 14, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patterned layer design for group III nitride layer growth
    Patent number: 9806228
    Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: October 31, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Semiconductor heterostructure with stress management
    Patent number: 9799793
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 24, 2017
    Assignee: Sensor Electronics Technology, Inc.
    Inventors: Daniel Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patterned Layer Design for Group III Nitride Layer Growth
    Publication number: 20170287698
    Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-Ill nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 5, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Optoelectronic Device with Modulation Doping
    Publication number: 20170263805
    Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.
    Type: Application
    Filed: May 8, 2017
    Publication date: September 14, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Group III Nitride Heterostructure for Optoelectronic Device
    Publication number: 20170256672
    Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.
    Type: Application
    Filed: May 23, 2017
    Publication date: September 7, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Disaster Recovery As A Service Using Virtualization Technique
    Publication number: 20170249221
    Abstract: Embodiments of the invention relate to recovering from a disaster associated with an information technology environment. An information technology environment is replicated to a service provider. A recovery plan is generated for the environment. The recovery plan includes two processes. In response to the service provider receiving a disaster recovery request associated with the environment, the service provider executes a disaster recovery protocol. The protocol includes simultaneously executes the first and second processes. The first process operates a workload in the form of one or more containers, and the second process is a background process that creates a replica of the environment. After completion of the replica creation, the workload is migrated to the replica.
    Type: Application
    Filed: February 29, 2016
    Publication date: August 31, 2017
    Applicant: International Business Machines Corporation
    Inventors: Rakesh Jain, Ramani R. Routray, Yang Song, Mu Qiao
  • Semiconductor layer including compositional inhomogeneities
    Patent number: 9748440
    Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: August 29, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Jinwei Yang, Remigijus Gaska, Mikhail Gaevski
  • Semiconductor heterostructure with stress management
    Patent number: 9735315
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: August 15, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Daniel Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Stress Relieving Semiconductor Layer
    Publication number: 20170229611
    Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
    Type: Application
    Filed: April 25, 2017
    Publication date: August 10, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
  • Patterned Substrate Design for Layer Growth
    Publication number: 20170229612
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • SCALABLE SENSOR FUSION AND AUTONOMOUS X-BY-WIRE CONTROL
    Publication number: 20170210376
    Abstract: An autonomous system for x-by-wire control includes processing nodes distributed and connected to one another. Sensors are connected to the processing nodes. Actuators are configured to directly control the autonomous system driven by and connected to the processing nodes for x-by-wire control. The processing nodes are configured to: partition and map processing tasks between the processing nodes, and merge and reduce results of individual processing tasks into an actionable table that specifies objectives for the autonomous system.
    Type: Application
    Filed: January 22, 2016
    Publication date: July 27, 2017
    Inventors: Rakesh Jain, Gabor Madl, Ramani R. Routray, Yang Song
  • Patterned layer design for group III nitride layer growth
    Patent number: 9691939
    Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: June 27, 2017
    Assignee: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Semiconductor Heterostructure with Stress Management
    Publication number: 20170179335
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 22, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Daniel Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • SUBSTITUTED 4-PHENYL PYRIDINE COMPOUNDS AS NON-SYSTEMIC TGR5 AGONISTS
    Publication number: 20170174718
    Abstract: The invention relates to non-systemic TGR5 agonist useful in the treatment of chemotherapy-induced diarrhea, diabetes, Type II diabetes, gestational diabetes, impaired fasting glucose, impaired glucose tolerance, insulin resistance, hyperglycemia, obesity, metabolic syndrome, ulcerative colitis, Crohn's disease, disorders associated with parenteral nutrition especially during short bowel syndrome, and irritable bowel syndrome (IBS), and other TGR5 associated diseases and disorders, having the Formula: where R1, R2, R2?, R3, R4, X1, X2, X3, X4, Q, and n are described herein.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 22, 2017
    Inventors: Jason Gustaf LEWIS, Michael Robert LEADBETTER, Jeremy CALDWELL, Dean DRAGOLI, Noah BELL, Jeffrey W. JACOBS, Patricia FINN, Rakesh JAIN, Tao CHEN, Matthew SIEGEL
  • Patterned layer design for group III nitride layer growth
    Patent number: 9680061
    Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: June 13, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur
  • Group III nitride heterostructure for optoelectronic device
    Patent number: 9660133
    Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: May 23, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Stress relieving semiconductor layer
    Patent number: 9653313
    Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: May 16, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
  • Optoelectronic device with modulation doping
    Patent number: 9653631
    Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: May 16, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska