Patents by Inventor Rakesh Jain

Rakesh Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9647168
    Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: May 9, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9634189
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 25, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Publication number: 20170104129
    Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Application
    Filed: December 23, 2016
    Publication date: April 13, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20170104132
    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 13, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
  • Publication number: 20170063654
    Abstract: In one embodiment, a method includes determining a first set of similarity metrics for a first storage environment, obtaining one or more second sets of similarity metrics from second storage environments that correspond with the first storage environment, calculating a similarity measurement score between the first storage environment and each of the second storage environments, and determining a set of similar storage environments from amongst the second storage environments based on the similarity measurement scores. Other methods, systems, and computer program products are presented according to more embodiments.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 2, 2017
    Inventors: Jorge D. Acuña, Pankaj S. Bavishi, Dachuan Huang, Rakesh Jain, Ramani R. Routray, Yang Song
  • Publication number: 20170005228
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Application
    Filed: September 15, 2016
    Publication date: January 5, 2017
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Daniel Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9537054
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: January 3, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Daniel D. Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9529631
    Abstract: Embodiments of the disclosure relate to automatic task execution on a mobile device. Aspects include identifying, by a processor, one or more hardware resources on the mobile device, identifying one or more patterns for each of the one or more hardware resources, and generating one or more composite patterns recognizable by the mobile device based on the one or more patterns. Aspects further include identifying one or more operations that can be performed via the mobile device and receiving, via a user-interface, an association between at least one of the one or more patterns and the one or more composite patterns and an execution of at least one of the one or more operations.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: December 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rakesh Jain, Ramani R. Routray, Yang Song, Chung-Hao Tan
  • Publication number: 20160343901
    Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Jinwei Yang, Remigijus Gaska, Mikhail Gaevski
  • Patent number: 9502509
    Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: November 22, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
  • Publication number: 20160336483
    Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. In one embodiment, the semiconductor layer is used to form an optoelectronic device.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 17, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Rakesh Jain, Michael Shur
  • Publication number: 20160330277
    Abstract: Embodiments relate to container migration and provisioning. An aspect includes receiving a request to migrate a composite application to a container-based environment. Another aspect includes determining a plurality of software components that make up the composite application. Another aspect includes determining communications patterns between the plurality of software components. Another aspect includes determining a containerization plan for the composite application based on the determined communications patterns. Another aspect includes creating a plurality of containers, and communications channels between the plurality of containers, for the software components of the composite application based on the containerization plan.
    Type: Application
    Filed: May 6, 2015
    Publication date: November 10, 2016
    Inventors: Rakesh Jain, Min Li, Ramani R. Routray, Yang Song, Chung-Hao Tan
  • Publication number: 20160322535
    Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Application
    Filed: July 18, 2016
    Publication date: November 3, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20160259669
    Abstract: Embodiments of the disclosure relate to automatic task execution on a mobile device. Aspects include identifying, by a processor, one or more hardware resources on the mobile device, identifying one or more patterns for each of the one or more hardware resources, and generating one or more composite patterns recognizable by the mobile device based on the one or more patterns. Aspects further include identifying one or more operations that can be performed via the mobile device and receiving, via a user-interface, an association between at least one of the one or more patterns and the one or more composite patterns and an execution of at least one of the one or more operations.
    Type: Application
    Filed: March 3, 2015
    Publication date: September 8, 2016
    Inventors: RAKESH JAIN, RAMANI R. ROUTRAY, YANG SONG, CHUNG-HAO TAN
  • Publication number: 20160247885
    Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 25, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
  • Publication number: 20160240739
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
    Type: Application
    Filed: April 26, 2016
    Publication date: August 18, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Patent number: 9406840
    Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 2, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Jinwei Yang, Remigijus Gaska, Mikhail Gaevski
  • Publication number: 20160218919
    Abstract: Provided are a method, system and program for publishing configuration patterns for storage resources and storage performance models from client systems to share with client systems in a network computing environment. A determination is made of a configuration pattern of storage resources within the client computing environment and storage performance metrics for the configuration pattern of storage resources within the client. At least one storage performance model is created based on the determined storage performance metrics. Information on the at least one storage performance model and the configuration pattern of the storage resources for which the storage performance metrics were determined are published to the service provider.
    Type: Application
    Filed: August 3, 2015
    Publication date: July 28, 2016
    Inventors: Rakesh Jain, Ramani R. Routray, Sumant Padbidri, Yang Song
  • Publication number: 20160219106
    Abstract: Provided are a computer program product, method, and system for providing information on published configuration patterns of storage resources to client systems in a network computing environment. Published configuration patterns of storage resources and storage performance models for the published configuration patterns are received from the client systems and stored in a catalog. The published storage performance models are based on storage performance and workloads realized at the configuration patterns of the storage resources. A determination is made from the catalog of at least one published configuration pattern that is similar to a requested configuration pattern requested by a client system according to at least one storage attribute. A result set is generated indicating the determined at least one published configuration pattern and the storage performance model and sent to the requesting client system.
    Type: Application
    Filed: August 5, 2015
    Publication date: July 28, 2016
    Inventors: Rakesh Jain, Ramani R. Routray, Sumant Padbidri, Yang Song
  • Publication number: 20160219107
    Abstract: Provided are a method, system and program for requesting storage performance models for a configuration pattern of storage resources to deploy at a client computing environment. A determination is made of a new configuration pattern of storage resources to deploy. A request is sent to a service provider with information on the new configuration pattern. A result set is received from the service provider having at least one provided configuration pattern having a degree of similarity to the new configuration pattern and a storage performance model for each of the provided configuration patterns. Each of the storage performance models indicate workload and performance characteristics for one of the provided configuration patterns. One of the provided configuration patterns is selected from the result set and the storage performance model for the selected configuration pattern is used to model performance at the client.
    Type: Application
    Filed: August 11, 2015
    Publication date: July 28, 2016
    Inventors: Rakesh Jain, Ramani R. Routray, Sumant Padbidri, Yang Song