Patents by Inventor Rakesh Jain

Rakesh Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10318160
    Abstract: A method and associated systems for a workload-aware thin-provisioning system that allocates physical storage to virtual resources from pools of physical storage volumes. The system receives constraints that limit the amount of storage that can be allocated from each pool and the total workload that can be directed to each pool. It also receives lists of previous workloads and allocations associated with each volume at specific times in the past. The system then predicts future workloads and allocation requirements for each volume by regressing linear equations derived from the received data. If the predicted values indicate that a pool will at a future time violate a received constraint, the system computes the minimum costs to move each volume of the offending pool to a less-burdened pool. It then selects the lowest-cost combination of volume and destination pool and then moves the selected volume to the selected pool.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: John J. Auvenshine, Rakesh Jain, James E. Olson, Mu Qiao, Ramani R. Routray, Stanley C. Wood
  • Patent number: 10313214
    Abstract: In one embodiment, a method includes determining a first set of similarity metrics for a first storage environment, the first set of similarity metrics being based on predetermined parameters related to the first storage environment, at least one of the predetermined parameters being relating to a redundancy of connections and devices in the first storage environment. In addition, the method includes obtaining a second set of similarity metrics for a second storage environment. Also, the method includes determining that the second storage environment is similar to the first storage environment by calculating a similarity measurement score between the sets of similarity metrics for the first and second storage environments. Moreover, the method includes re-aligning the first storage environment according to one or more identified aspects of the second storage environment that improve performance of the first storage environment.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jorge D. Acuña, Pankaj S. Bavishi, Dachuan Huang, Rakesh Jain, Ramani R. Routray, Yang Song
  • Patent number: 10297460
    Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 21, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
  • Patent number: 10284647
    Abstract: Provided are a computer program product, method, and system for providing information on published configuration patterns of storage resources to client systems in a network computing environment. Published configuration patterns of storage resources and storage performance models for the published configuration patterns are received from the client systems and stored in a catalog. The published storage performance models are based on storage performance and workloads realized at the configuration patterns of the storage resources. A determination is made from the catalog of at least one published configuration pattern that is similar to a requested configuration pattern requested by a client system according to at least one storage attribute. A result set is generated indicating the determined at least one published configuration pattern and the storage performance model and sent to the requesting client system.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rakesh Jain, Ramani R. Routray, Sumant Padbidri, Yang Song
  • Patent number: 10248320
    Abstract: A method and associated systems for a workload-aware thin-provisioning system that allocates physical storage to virtual resources from pools of physical storage volumes. The system receives constraints that limit the amount of storage that can be allocated from each pool and the total workload that can be directed to each pool. It also receives lists of previous workloads and allocations associated with each volume at specific times in the past. The system then predicts future workloads and allocation requirements for each volume by regressing linear equations derived from the received data. If the predicted values indicate that a pool will at a future time violate a received constraint, the system computes the minimum costs to move each volume of the offending pool to a less-burdened pool. It then selects the lowest-cost combination of volume and destination pool and then moves the selected volume to the selected pool.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: John J. Auvenshine, Rakesh Jain, James E. Olson, Mu Qiao, Ramani R. Routray, Stanley C. Wood
  • Patent number: 10243100
    Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: March 26, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Jinwei Yang, Remigijus Gaska, Mikhail Gaevski
  • Publication number: 20190078115
    Abstract: Soybean plants comprising event SYHT0H2, methods of detecting and using the same, and soybean plants comprising a heterologous insert at the same site as SYHT0H2.
    Type: Application
    Filed: October 25, 2018
    Publication date: March 14, 2019
    Applicant: SYNGENTA PARTICIPATIONS AG
    Inventors: John Daniel Hipskind, Kristina Burgin, Rakesh Jain, Karolyn Terpstra, Marina Sigareva, Annick Jeanne De Framond, Becky Breitinger, Vance Cary Kramer, Weining Gu
  • Publication number: 20190073135
    Abstract: A method and associated systems for a workload-aware thin-provisioning system that allocates physical storage to virtual resources from pools of physical storage volumes. The system receives constraints that limit the amount of storage that can be allocated from each pool and the total workload that can be directed to each pool. It also receives lists of previous workloads and allocations associated with each volume at specific times in the past. The system then predicts future workloads and allocation requirements for each volume by regressing linear equations derived from the received data. If the predicted values indicate that a pool will at a future time violate a received constraint, the system computes the minimum costs to move each volume of the offending pool to a less-burdened pool. It then selects the lowest-cost combination of volume and destination pool and then moves the selected volume to the selected pool.
    Type: Application
    Filed: November 6, 2018
    Publication date: March 7, 2019
    Inventors: John J. Auvenshine, Rakesh Jain, James E. Olson, Mu Qiao, Ramani R. Routray, Stanley C. Wood
  • Publication number: 20190057180
    Abstract: Performing design optimization using an augmented reality system. Baseline data comprising baseline sensor data and baseline user input data is received by a computer system. An interactive baseline design optimization problem based on the baseline data is generated by the computer system. The baseline interactive optimization problem is transmitted by the computer system to the augmented reality system. Refined data comprising refined sensor data and refined user input data is received by the computer system. An interactive refined optimization problem based on the refined data and the baseline data is generated by the computer system. The interactive refined optimization problem is transmitted by the computer system to the augmented reality system.
    Type: Application
    Filed: August 18, 2017
    Publication date: February 21, 2019
    Inventors: Luis Angel D. Bathen, Simon-Pierre M. C. Genot, Rakesh Jain, Sunhwan Lee, Mu Qiao, Ramani R. Routray
  • Publication number: 20190057181
    Abstract: Performing design optimization using an augmented reality system. Baseline data comprising baseline sensor data and baseline user input data is received by a computer system. An interactive baseline design optimization problem based on the baseline data is generated by the computer system. The baseline interactive optimization problem is transmitted by the computer system to the augmented reality system. Refined data comprising refined sensor data and refined user input data is received by the computer system. An interactive refined optimization problem based on the refined data and the baseline data is generated by the computer system. The interactive refined optimization problem is transmitted by the computer system to the augmented reality system.
    Type: Application
    Filed: December 21, 2017
    Publication date: February 21, 2019
    Inventors: Luis Angel D. Bathen, Simon-Pierre M. C. Genot, Rakesh Jain, Sunhwan Lee, Mu Qiao, Ramani R. Routray
  • Patent number: 10211048
    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: February 19, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Wenhong Sun, Rakesh Jain, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
  • Patent number: 10199536
    Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10199531
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Daniel Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10184134
    Abstract: Soybean plants comprising event SYHT0H2, methods of detecting and using the same, and soybean plants comprising a heterologous insert at the same site as SYHT0H2.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: January 22, 2019
    Assignee: Syngenta Participations AG
    Inventors: John Daniel Hipskind, Kristina Burgin, Rakesh Jain, Karolyn Terpstra, Marina Sigareva, Annick Jeanne De Framond, Becky Breitinger, Vance Cary Kramer, Weining Gu
  • Publication number: 20190019917
    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 17, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur, Brandon Robinson
  • Publication number: 20190006553
    Abstract: Semiconductor structures formed with annealing for use in the fabrication of optoelectronic devices. The semiconductor structures can include a substrate, a nucleation layer and a buffer layer. The nucleation layer and the buffer layer can be epitaxially grown and then annealed. The temperature of the annealing of the nucleation layer and the buffer layer is greater than the temperature of the epitaxial growth of the layers. The annealing reduces the dislocation density in any subsequent layers that are added to the semiconductor structures. A desorption minimizing layer epitaxially grown on the buffer layer can be used to minimize desorption during the annealing of the layer which also aids in curtailing dislocation density and cracks in the semiconductor structures.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 3, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov
  • Patent number: 10169174
    Abstract: Embodiments of the invention relate to recovering from a disaster associated with an information technology environment. An information technology environment is replicated to a service provider. A recovery plan is generated for the environment. The recovery plan includes two processes. In response to the service provider receiving a disaster recovery request associated with the environment, the service provider executes a disaster recovery protocol. The protocol includes simultaneously executes the first and second processes. The first process operates a workload in the form of one or more containers, and the second process is a background process that creates a replica of the environment. After completion of the replica creation, the workload is migrated to the replica.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Rakesh Jain, Ramani R. Routray, Yang Song, Mu Qiao
  • Patent number: 10159254
    Abstract: The present invention relates, inter alia, to a method of improving the tolerance of a plant, which has been genetically engineered to over express a p-hydroxyphenylpyruvate dioxygenase (HPPD), to a HPPD inhibiting herbicide, said method comprising applying to said plant a water-soluble iron-containing compound. The present invention further relates to a method of selectively controlling weeds at a locus, the locus comprising weeds and crop plants, the crop plants having been genetically engineered to overexpress a HPPD which confers tolerance to a HPPD-inhibiting herbicide, the method comprising application to the locus of (i) a weed controlling amount of a HPPD-inhibiting herbicide and (ii) a water-soluble iron-containing compound. The present invention further relates to herbicidal compositions comprising a HPPD-inhibiting herbicide and a water-soluble iron-containing compound.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: December 25, 2018
    Assignee: Syngenta Participations AG
    Inventors: Rakesh Jain, Brett Robert Miller, Gordan Dean Vail, Bryan James Ulmer
  • Patent number: 10158044
    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 18, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
  • Patent number: 10153396
    Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 11, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska