Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal-ferroelectric-metal-insulator-semiconductor structures and methods of manufacture. The structure includes a plurality of top gate structures and a bottom gate structure comprising a metal material shared with the plurality of top gate structures.

Abstract: The disclosure provides a structure with a buried doped region for coupling a source line contact to the gate structure of a memory cell. A structure according to the disclosure includes a memory cell having a gate structure extending in a first lateral direction over a substrate. A buried doped region is within the substrate and extends in a second lateral direction from below the gate structure to a portion of the substrate laterally distal to the gate structure. A source line contact is on the portion of the substrate laterally distal to the gate structure. The buried doped region couples the source line contact to the gate structure of the memory cell through a lower surface of the gate structure.

Abstract: The present disclosure relates to a method for developing a design of an electronic circuit system in one or more Electronic Design Automation (EDA) environments. The method comprises: receiving data indicative of an event related to a specific point in time during development of the design of the electronic circuit system using a first software tool. A development action may be determined based on the event. Design data descriptive of a state of the design at the point in time, and a library setup descriptive of libraries used by the first software tool to provide the design at that state may be determined. A design snapshot data structure comprising entries representing the design data and the library setup may be created. The design snapshot data structure may be shared with a second software tool for enabling execution of the development action using the second software tool.

Abstract: A mixture contains at least one amino-regulated polyether block amide (PEBA) and at least one poly(meth)acrylate selected from poly(meth)acrylimides, polyalkyl(meth)acrylates, and mixtures thereof. The mass ratio of PEBA to poly(meth)acrylate is 95:5 to 60:40. The polyalkyl(meth)acrylate contains 80% by weight to 99% by weight of methyl methacrylate (MMA) units and 1% by weight to 20% by weight of C1-C10-alkyl acrylate units, based on the total weight of polyalkyl(meth)acrylate. The mixture can be processed to give foamed mouldings. The mouldings can be used in footwear soles, stud material, insulation or insulating material, damping components, lightweight components, or in a sandwich structure.

Abstract: Disclosed are embodiments of a semiconductor device and method of forming the device. The device includes a gate with first and second sections on a semiconductor layer. The first section includes first gate dielectric and gate conductor layers and an optional additional gate conductor layer on the first gate conductor layer. The second section includes second gate dielectric and gate conductor layers on the semiconductor layer and further extending onto the top of the first gate conductor layer. The second gate dielectric layer is thinner than the first gate dielectric layer. A gate sidewall spacer is on the first gate conductor layer positioned laterally to a sidewall of the second section (e.g., between the sidewall and the optional additional gate conductor layer). The first and second sections are either electrically connected for biasing with the gate bias voltage or electrically isolated for biasing with different gate bias voltages.

Abstract: A process can be used for manufacturing a coloured moulding composition with an improved optical appearance and a particularly high thermal stability. The process involves providing a thermoplastic polymer and adding a colouring preparation, or a liquid composition or a master batch containing the colouring preparation. Injection moulded parts and extruded parts can be composed of the coloured moulding composition.

Abstract: Poly(meth)acrylate impact modifiers having at least one multiphase alkyl (meth)acrylate emulsion polymer with at least one multivalent metal ion, and a defined amount of alkali metal ions improve the optical properties of moulding compositions produced thereof. One improved property is a high transparency after hot water storage. A method for producing the poly(meth)acrylate impact modifiers include the preparation of at least one multiphase alkyl (meth)acrylate polymer via emulsion polymerization, the coagulation and mechanical dewatering of the obtained latex.

Abstract: Present embodiments relate to an active insulated container which may be used in a vehicle. More specifically, but without limitation, present embodiments relate to active insulated containers which may be mounted in a vehicle and which creates a positive pressure upon entry of water into one or more ducts to preclude entrance of water into a thermal engine enclosure housing the thermal engine, even when mounted at a lower elevation of the vehicle.

Abstract: A computer implemented method for a multi-layer integrated circuit routing tool connecting sources with nets to sinks in a hierarchical multi-layer integrated circuit design environment, the method including creating a cycle reach table containing a first set of information parameters for two dimensional nets per metal layer combination, creating a repeater reach table containing a second set of information parameters per constraint class, preparing a working list of nets, preparing a list of blocks larger than repeater reach dimensions, connecting a source pin to a sink pin on preassigned metal layers, by routing the net based on the given constraint class.

Abstract: A mixture contains at least one polyether block amide (PEBA) and at least one poly(meth)acrylate, selected from poly(meth)acrylimides, poly-alkyl(meth)acrylates, and mixtures thereof. The mass ratio of PEBA to poly(meth)acrylate is 95:5 to 60:40. The polyalkyl(meth)acrylate contains 80% by weight to 99% by weight of methyl methacrylate (MMA) units and 1% by weight to 20% by weight of C1-C10-alkyl acrylate units, based on the total weight of polyalkyl(meth)acrylate. The mixture can be processed to give foamed mouldings. The mouldings can be used in footwear soles, stud material, insulation or insulating material, damping components, lightweight components, or in a sandwich structure.

Abstract: Polymer compositions are made based on imidated polyalkyl (meth)acrylate, especially imidated polymethyl methacrylate. The polymer composition includes a polymer matrix A and at least one tribological additive B, especially selected from organic or inorganic solid hardening particles. The polymer compositions and formed articles made thereof exhibit low friction coefficients and high wear resistance even at elevated temperatures. They can advantageously be used in tribological application, in replacement of high-performance materials, such as polyether ether ketone (PEEK).

Abstract: Disclosed are embodiments of a semiconductor device and method of forming the device. The device includes a gate with first and second sections on a semiconductor layer. The first section includes first gate dielectric and gate conductor layers and an optional additional gate conductor layer on the first gate conductor layer. The second section includes second gate dielectric and gate conductor layers on the semiconductor layer and further extending onto the top of the first gate conductor layer. The second gate dielectric layer is thinner than the first gate dielectric layer. A gate sidewall spacer is on the first gate conductor layer positioned laterally to a sidewall of the second section (e.g., between the sidewall and the optional additional gate conductor layer). The first and second sections are either electrically connected for biasing with the gate bias voltage or electrically isolated for biasing with different gate bias voltages.

Abstract: The disclosure provides a structure with a buried doped region for coupling a source line contact to the gate structure of a memory cell. A structure according to the disclosure includes a memory cell having a gate structure extending in a first lateral direction over a substrate. A buried doped region is within the substrate and extends in a second lateral direction from below the gate structure to a portion of the substrate laterally distal to the gate structure. A source line contact is on the portion of the substrate laterally distal to the gate structure. The buried doped region couples the source line contact to the gate structure of the memory cell through a lower surface of the gate structure.

Abstract: A park lock mechanism for a motor vehicle includes a park lock pawl for selectively forming a form-locking connection to a lock region, the park lock mechanism having a locking mode, in which the park lock pawl is moved into a locking position, and a driving mode, in which the park lock pawl is moved into a driving position. The park lock pawl is pivotable about a pawl axis from the locking position into the driving position. A locking pawl spring device preloads the park lock pawl into the driving position. A locking pawl actuation device has a locking pawl actuator with a locking pawl actuator shaft and has a locking pawl cone, the locking pawl cone being movable along a cone axis by the locking pawl actuator. The cone axis is parallel to the pawl axis. The locking pawl cone is movable along the cone axis between a cone driving position and a cone locking position.

Abstract: A computer implemented method for a multi-layer integrated circuit routing tool connecting sources with nets to sinks in a hierarchical multi-layer integrated circuit design environment, the method including creating a cycle reach table containing a first set of information parameters for two dimensional nets per metal layer combination, creating a repeater reach table containing a second set of information parameters per constraint class, preparing a working list of nets, preparing a list of blocks larger than repeater reach dimensions, connecting a source pin to a sink pin on preassigned metal layers, by routing the net based on the given constraint class.

Abstract: A park lock mechanism for a motor vehicle includes a park lock pawl for selectively forming a form-locking connection to a lock region, the park lock mechanism having a locking mode, in which the park lock pawl is moved into a locking position, and a driving mode, in which the park lock pawl is moved into a driving position. The park lock pawl is pivotable about a pawl axis from the locking position into the driving position. A locking pawl spring device preloads the park lock pawl into the driving position. A locking pawl actuation device has a locking pawl actuator with a locking pawl actuator shaft and has a locking pawl cone, the locking pawl cone being movable along a cone axis by the locking pawl actuator. The cone axis is parallel to the pawl axis. The locking pawl cone is movable along the cone axis between a cone driving position and a cone locking position.

Abstract: A nonvolatile memory device is provided, the device comprising a ferroelectric memory capacitor arranged over a first active region contact of a first transistor and a gate contact of a second transistor, whereby the ferroelectric memory capacitor at least partially overlaps a gate of the first transistor.

Abstract: A process can be used for manufacturing a coloured moulding composition with an improved optical appearance and a particularly high thermal stability. The process involves providing a thermoplastic polymer and adding a colouring preparation, or a liquid composition or a master batch containing the colouring preparation. Injection moulded parts and extruded parts can be composed of the coloured moulding composition.

Abstract: A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.

Abstract: A nonvolatile memory device is provided, the device comprising a ferroelectric memory capacitor arranged over a first active region contact of a first transistor and a gate contact of a second transistor, whereby the ferroelectric memory capacitor at least partially overlaps a gate of the first transistor.