Abstract: A method is provided for operating a trace procedure, which traces execution of a computer program, where the program uses different callable modules. A program stack is used to store trace buffer information and an error state, and the modules include calls of the trace procedure. The method includes: (i) when entering execution of a module, storing the current write position of the trace buffer and a cleared error flag in the current frame of the stack; (ii) in case of an error condition during execution of the program, setting the error flag in the current frame; and (iii) when leaving execution of a module, determining if the error flag is set, and if not, then rewinding the trace buffer to the write position stored in the current frame, and deleting the current write position of the trace buffer and the error flag from the stack.

Abstract: A method is provided for operating a trace procedure, which traces execution of a computer program, where the program uses different callable modules. A program stack is used to store trace buffer information and an error state, and the modules include calls of the trace procedure. The method includes: (i) when entering execution of a module, storing the current write position of the trace buffer and a cleared error flag in the current frame of the stack; (ii) in case of an error condition during execution of the program, setting the error flag in the current frame; and (iii) when leaving execution of a module, determining if the error flag is set, and if not, then rewinding the trace buffer to the write position stored in the current frame, and deleting the current write position of the trace buffer and the error flag from the stack.

Abstract: A semiconductor device structure includes an active region positioned in a semiconductor substrate and a gate structure of a transistor positioned above the active region. The gate structure includes a gate insulating layer, a gate metal layer positioned above the gate insulating layer and a trimmed gate electrode material layer positioned above the gate metal layer. A length of at least a portion of the trimmed gate electrode material layer in a gate length direction of the transistor is less than a length of at least the gate metal layer in the gate length direction.

Abstract: The present disclosure provides in one aspect for a semiconductor device structure which may be formed by providing source/drain regions within a semiconductor substrate in alignment with a gate structure formed over the semiconductor substrate, wherein the gate structure has a gate electrode structure, a first sidewall spacer and a second sidewall spacer, the first sidewall spacer covering sidewall surfaces of the gate electrode structure and the sidewall spacer being formed on the first sidewall spacer. Furthermore, forming the semiconductor device structure may include removing the second sidewall spacer so as to expose the first sidewall spacer, forming a third sidewall spacer on a portion of the first sidewall spacer such that the first sidewall spacer is partially exposed, and forming silicide regions in alignment with the third sidewall spacer in the source/drain regions.

Abstract: A method of manufacturing a semiconductor device is provided including forming replacement gates over a semiconductor layer, forming sidewall spacers at sidewalls of the replacement gates, forming a dielectric layer in interspaces between the sidewall spacers of neighboring replacement gates, removing the replacement gates and sidewall spacers to form openings in the dielectric layer, and forming gate electrodes in the openings.

Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

Abstract: The present disclosure provides a method of forming a semiconductor device and a semiconductor device. An SOI substrate portion having a semiconductor layer, a buried insulating material layer and a bulk substrate is provided, wherein the buried insulating material layer is interposed between the semiconductor layer and the bulk substrate. The SOI substrate portion is subsequently patterned so as to form a patterned bi-layer stack on the bulk substrate, which bi-layer stack comprises a patterned semiconductor layer and a patterned buried insulating material layer. The bi-layer stack is further enclosed with a further insulating material layer and an electrode material is formed on and around the further insulating material layer. Herein a gate electrode is formed by the bulk substrate and the electrode material such that the gate electrode substantially surrounds a channel portion formed by a portion of the patterned buried insulating material layer.

Abstract: The present disclosure provides a method of forming a semiconductor device and a semiconductor device. An SOI substrate portion having a semiconductor layer, a buried insulating material layer and a bulk substrate is provided, wherein the buried insulating material layer is interposed between the semiconductor layer and the bulk substrate. The SOI substrate portion is subsequently patterned so as to form a patterned bi-layer stack on the bulk substrate, which bi-layer stack comprises a patterned semiconductor layer and a patterned buried insulating material layer. The bi-layer stack is further enclosed with a further insulating material layer and an electrode material is formed on and around the further insulating material layer. Herein a gate electrode is formed by the bulk substrate and the electrode material such that the gate electrode substantially surrounds a channel portion formed by a portion of the patterned buried insulating material layer.

Abstract: Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure.

Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. A first sacrificial oxide layer is formed overlying the semiconductor substrate and a first implant mask is patterned overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate, through the first sacrificial oxide layer. The first implant mask and the first sacrificial oxide layer are removed after implanting the conductivity determining ions into the semiconductor substrate.

Abstract: The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.

Abstract: A method to implant dopants onto fin-type field-effect-transistor (FINFET) fin surfaces with uniform concentration and depth levels of the dopants and the resulting device are disclosed. Embodiments include a method for pulsing a dopant perpendicular to an upper surface of a substrate, forming an implantation beam pulse; applying an electric or a magnetic field to the implantation beam pulse to effectuate a curvilinear trajectory path of the implantation beam pulse; and implanting the dopant onto a sidewall surface of a target FINFET fin on the upper surface of the substrate via the curvilinear trajectory path of the implantation beam pulse.

Abstract: The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.

Abstract: The present disclosure provides in one aspect for a semiconductor device structure which may be formed by providing source/drain regions within a semiconductor substrate in alignment with a gate structure formed over the semiconductor substrate, wherein the gate structure has a gate electrode structure, a first sidewall spacer and a second sidewall spacer, the first sidewall spacer covering sidewall surfaces of the gate electrode structure and the sidewall spacer being formed on the first sidewall spacer. Furthermore, forming the semiconductor device structure may include removing the second sidewall spacer so as to expose the first sidewall spacer, forming a third sidewall spacer on a portion of the first sidewall spacer such that the first sidewall spacer is partially exposed, and forming silicide regions in alignment with the third sidewall spacer in the source/drain regions.

Abstract: The invention concerns a group of vessels (24), having an unmanned surface vessel (3) and an unmanned underwater vessel (1, 1a), wherein the underwater vessel comprises a location device, in particular a sonar device, for sensing location data (12) in the underwater area and one evaluation unit or more evaluation units, and the evaluation unit or the evaluation units are arranged in such a manner that these comprise detection means (20) for detecting (14) a contact (MILEC) with the aid of the sensed location data (12) and with classification means (21) for classifying (15) the detected contact (MILEC) as a mine-like contact (MILCO) or non mine-like contact (NONMILCO), whereby classification is accomplished by comparing the contact (MILEC) with known mine information so that a mine-like contact (MILCO) can be identified as a mine contact (MINE) or as another object (NOMBO).

Abstract: Forming a poly-Si device including pulling back spacers prior to silicidation and the resulting device are provided. Embodiments include forming two poly-Si gate stacks on an upper surface of a substrate; forming a hardmask over the second poly-Si gate stack; forming eSiGe with a silicon cap at opposite sides of the first poly-Si gate stack; removing the hardmask; forming nitride spacers at opposite sides of each of the poly-Si gate stacks; forming deep source/drain regions at opposite sides of the second poly-Si gate stack; forming a wet gap fill layer around each of the poly-Si gate stacks to a thickness less than the poly-Si gate stack height from the substrate's upper surface; removing an upper portion of the nitride spacers down to the height of the wet gap fill layer followed by removing the wet gap fill layer; and performing silicidation of the deep source/drain regions and the silicon cap.

Abstract: Forming a poly-Si device including pulling back spacers prior to silicidation and the resulting device are provided. Embodiments include forming two poly-Si gate stacks on an upper surface of a substrate; forming a hardmask over the second poly-Si gate stack; forming eSiGe with a silicon cap at opposite sides of the first poly-Si gate stack; removing the hardmask; forming nitride spacers at opposite sides of each of the poly-Si gate stacks; forming deep source/drain regions at opposite sides of the second poly-Si gate stack; forming a wet gap fill layer around each of the poly-Si gate stacks to a thickness less than the poly-Si gate stack height from the substrate's upper surface; removing an upper portion of the nitride spacers down to the height of the wet gap fill layer followed by removing the wet gap fill layer; and performing silicidation of the deep source/drain regions and the silicon cap.

Abstract: The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.

Abstract: FinFET devices with epitaxially grown fins and methods for fabricating them are provided. Embodiments include forming at least two shallow trench isolation (STI) regions, filled with dielectric material, adjacent to but separate from each other in a silicon substrate; epitaxially growing a silicon-based layer between each adjacent pair of STI regions to form a fin with a non-rectangular cross-section extending from each STI region to each adjacent STI region; forming a gate oxide over and perpendicular to each fin; and forming a gate electrode over the gate oxide to form a FinFET.

Abstract: When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material.