Abstract: A system, apparatus, and method of testing a plurality of test circuits is disclosed that includes inputting experiment data to the plurality of test circuits; applying a control signal to each of the plurality of test circuits to control application of the experiment data to the plurality of test circuits; and shifting the control signal in response to applying the control signal to each of the plurality of test circuits so that a different bit of the control signal is applied to each of the plurality of test circuits. The method in an aspect further comprises reading out a data out signal from each of the plurality of test circuits; and shifting the data out signal in response to reading out the data out signal from each of the plurality of test circuits.

Abstract: A screw pump with a housing; a housing cover; at least one idler screw held in a bore in the housing; and a bushing arranged on the housing cover with a receiving space bounded by a cylindrical flange, into which one end of the idler screw engages; wherein the bushing has an opening in its base, through which a fluid, supplied by a feed channel in the cover, can be supplied from the end opposite the idler screw under pressure to the end surface of the idler screw, wherein the bushing engages with radial play in a receptacle in the cover and comprises a radial flange, by which it is supported axially on the housing; and wherein at a least certain part of the ring-shaped flange of the bushing engages in the bore and is accommodated therein with play.

Abstract: Light scattering polymeric compositions have improved scattering efficiency and improved mechanical properties. The compositions include a polymeric matrix material and at least two different kinds of scattering particles uniformly dispersed therein.

Abstract: A modular system for producing a screw spindle pump having a housing with a drive spindle therein and at least one running spindle meshing with the drive spindle, including: a plurality of housing components including a basic housing component exhibiting a fluid inlet for the formation of a basic pump chamber, a housing pressure component exhibiting a fluid outlet, bearing the drive spindle for creating a pressure chamber, a housing cover arranged on the basic housing part for supporting running spindle, and identical intermediate housing components arrangeable in any number between the basic housing component and the housing pressure component and form an additional pump chamber in each case; and a plurality of running spindle elements including at least one running spindle base element arranged in the basic housing component, and identical running spindle extension elements arranged in the intermediate housing components.

Abstract: A system, apparatus, and method of testing a plurality of test circuits is disclosed that includes inputting experiment data to the plurality of test circuits; applying a control signal to each of the plurality of test circuits to control application of the experiment data to the plurality of test circuits; and shifting the control signal in response to applying the control signal to each of the plurality of test circuits so that a different bit of the control signal is applied to each of the plurality of test circuits. The method in an aspect further comprises reading out a data out signal from each of the plurality of test circuits; and shifting the data out signal in response to reading out the data out signal from each of the plurality of test circuits.

Abstract: A memory device structure includes a wafer substrate and a magnetic tunnel junction (MTJ) positioned above an upper surface of the wafer substrate. The MTJ includes a first magnetic layer, a second magnetic layer laterally adjacent the first magnetic layer, and a nonmagnetic layer interposed between the first and second magnetic layers, wherein the first magnetic layer, the nonmagnetic layer and the second magnetic layer comprise a substantially vertical layer stack that extends along a first direction that is substantially perpendicular to the upper surface of the wafer substrate. A first contact is electrically coupled to the first magnetic layer and a second contact is electrically coupled to the second magnetic layer.

Abstract: A process is for preparing polymeric particles for use as impact modifiers in curable (meth)acrylic resin compositions. Further, the process relates to a cured (meth)acrylic resin composition, in particular to adhesive or coating materials containing polymeric particles dispersed in a cured (meth)acrylic resin matrix. Said composition can be advantageously used as an adhesive, coating or a composite material.

Abstract: A polymeric particle has an average diameter from 300 nm to 1000 nm and includes an outer layer, containing a cross-linked polymer A, and a first inner layer, containing a cross-linked polymer B, distinct from the cross-linked polymer A. The cross-linked polymer A is obtainable by emulsion polymerisation of a reaction mixture including at least one (meth)acrylic monomer, a cross-linking monomer A, a polymerisation initiator and a chain transfer agent.

Abstract: A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. The first and second gates extend across the first nonvolatile memory cells, the second gate partially overlapping the first gate, and the third and fourth gates extend across the second nonvolatile memory cells, the fourth gate partially overlapping the third gate. Each of the first, second, third, and fourth gates has an end portion that is positioned in the edge cell, and the edge cell includes a protection layer that is positioned over the end portions of the first, second, third, and fourth gates and covers an end face of the second and fourth gates.

Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.

Abstract: A method is provided for operating a trace procedure, which traces execution of a computer program, where the program uses different callable modules. A program stack is used to store trace buffer information and an error state, and the modules include calls of the trace procedure. The method includes: (i) when entering execution of a module, storing the current write position of the trace buffer and a cleared error flag in the current frame of the stack; (ii) in case of an error condition during execution of the program, setting the error flag in the current frame; and (iii) when leaving execution of a module, determining if the error flag is set, and if not, then rewinding the trace buffer to the write position stored in the current frame, and deleting the current write position of the trace buffer and the error flag from the stack.

Abstract: An integrated circuit product includes a silicon-on-insulator (SOI) substrate and a flash memory device positioned in a first area of the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device. The flash transistor device includes a floating gate, an insulating layer positioned above the floating gate, and a control gate positioned above the insulating layer, wherein the floating gate includes a portion of the semiconductor layer. The read transistor device includes a gate dielectric layer positioned above the semiconductor bulk substrate and a read gate electrode positioned above the gate dielectric layer.

Abstract: A screw pump with a housing; a housing cover; at least one idler screw held in a bore in the housing; and a bushing arranged on the housing cover with a receiving space bounded by a cylindrical flange, into which one end of the idler screw engages; wherein the bushing has an opening in its base, through which a fluid, supplied by a feed channel in the cover, can be supplied from the end opposite the idler screw under pressure to the end surface of the idler screw, wherein the bushing engages with radial play in a receptacle in the cover and comprises a radial flange, by which it is supported axially on the housing; and wherein at a least certain part of the ring-shaped flange of the bushing engages in the bore and is accommodated therein with play.

Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.

Abstract: Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer.

Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.

Abstract: A modular system for producing a screw spindle pump having a housing with a drive spindle therein and at least one running spindle meshing with the drive spindle, including: a plurality of housing components including a basic housing component exhibiting a fluid inlet for the formation of a basic pump chamber, a housing pressure component exhibiting a fluid outlet, bearing the drive spindle for creating a pressure chamber, a housing cover arranged on the basic housing part for supporting running spindle, and identical intermediate housing components arrangeable in any number between the basic housing component and the housing pressure component and form an additional pump chamber in each case; and a plurality of running spindle elements including at least one running spindle base element arranged in the basic housing component, and identical running spindle extension elements arranged in the intermediate housing components.

Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.

Abstract: Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. A hardmask layer is formed on the first gate dielectric layer in the first area of the semiconductor layer. A gate stack layer is formed on the semiconductor layer in a second area and on the hardmask layer in the first area of the semiconductor layer. The hardmask layer separates the gate stack layer from the first gate dielectric layer on the first area of the semiconductor layer.