Abstract: A method to implant dopants onto fin-type field-effect-transistor (FINFET) fin surfaces with uniform concentration and depth levels of the dopants and the resulting device are disclosed. Embodiments include a method for pulsing a dopant perpendicular to an upper surface of a substrate, forming an implantation beam pulse; applying an electric or a magnetic field to the implantation beam pulse to effectuate a curvilinear trajectory path of the implantation beam pulse; and implanting the dopant onto a sidewall surface of a target FINFET fin on the upper surface of the substrate via the curvilinear trajectory path of the implantation beam pulse.

Abstract: Integrated circuits and methods for manufacturing the same are provided. A method for manufacturing an integrated circuit includes forming a first and second STI insulator in a substrate, and bowing a substrate surface between the first and second STI insulators. A transistor is formed between the first and second STI insulators.

Abstract: FinFET devices with epitaxially grown fins and methods for fabricating them are provided. Embodiments include forming at least two shallow trench isolation (STI) regions, filled with dielectric material, adjacent to but separate from each other in a silicon substrate; epitaxially growing a silicon-based layer between each adjacent pair of STI regions to form a fin with a non-rectangular cross-section extending from each STI region to each adjacent STI region; forming a gate oxide over and perpendicular to each fin; and forming a gate electrode over the gate oxide to form a FinFET.

Abstract: Disclosed is an integrated circuit product comprised of a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only the second PMOS active region has a silicon germanium layer formed thereon, a first PMOS device formed in and above the first PMOS active region, the first PMOS device having a first gate structure, and a second PMOS device formed in and above the second PMOS active region, the second PMOS device having a second gate structure disposed on the silicon germanium layer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.

Abstract: One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor.

Abstract: The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.

Abstract: In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment.

Abstract: Generally, the subject matter disclosed herein relates to various methods of making a capacitor with a sealing liner and a semiconductor device including such a capacitor. In one example, the method includes forming a layer of insulating material, forming a capacitor opening in the layer of insulating material, forming a sealing liner on the sidewalls of the capacitor opening and forming a first metal layer in the capacitor opening and on the sealing liner by performing a process using a precursor having a minimum particle size, wherein the sealing liner is made of a material having an opening size that is less than the minimum particle size of the precursor.

Abstract: A method of forming an inductor in a crystal semiconductor layer is provided, including generating an ion beam, directing the ion beam to a surface of the crystal semiconductor layer, applying a magnetic field to the ion beam to generate a helical motion of the ions and forming a three-dimensional helical structure in the crystal semiconductor layer by means of the ions of the ion beam.

Abstract: A method of forming a semiconductor device is provided including the steps of forming first and second PMOS transistor devices, wherein the first PMOS transistor devices are low, standard or high voltage threshold transistor devices and the second PMOS transistor devices are super high voltage threshold transistor devices, and wherein forming the first PMOS transistor devices includes implanting dopants to form source and drain junctions of the first PMOS transistor devices and performing a thermal anneal of the first PMOS transistor devices after implanting the dopants, and forming the second PMOS transistor devices includes implanting dopants to form source and drain junctions of the second PMOS transistor devices after performing the thermal anneal of the first PMOS transistor devices.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment of a method for fabricating integrated circuits, a P-type gate electrode structure and an N-type gate electrode structure are formed overlying a semiconductor substrate. The gate electrode structures each include a gate electrode that overlies a gate dielectric layer and a nitride cap that overlies the gate electrode. Conductivity determining ions are implanted into the semiconductor substrate using the P-type gate electrode structure and the N-type gate electrode structure as masks to form a source region and a drain region for the P-type gate electrode structure and the N-type gate electrode structure. The nitride cap remains overlying the N-type gate electrode structure during implantation of the conductivity determining ions into the semiconductor substrate to form the source region and the drain region for the N-type gate electrode structure.

Abstract: A known problem when manufacturing transistors is the stress undesirably introduced by the spacers into the transistor channel region. In order to solve this problem, the present invention proposes an ion implantation aimed at relaxing the stress of the spacer materials. The relax implantation is performed after the spacer has been completely formed. The relax implantation may be performed after a silicidation process or after an implantation step in the source and drain regions followed by an activation annealing and before performing the silicidation process.

Abstract: Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion.

Abstract: In a replacement gate approach, the exposure of the placeholder material of the gate electrode structures may be accomplished on the basis of an etch process, thereby avoiding the introduction of process-related non-uniformities, which are typically associated with a complex polishing process for exposing the top surface of the placeholder material. In some illustrative embodiments, the placeholder material may be exposed by an etch process based on a sacrificial mask material.

Abstract: When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer.

Abstract: The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.

Abstract: Methods and apparatus are provided for an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator.

Abstract: The invention concerns a group of vessels (24), having an unmanned surface vessel (3) and an unmanned underwater vessel (1, 1a), wherein the underwater vessel comprises a location device, in particular a sonar device, for sensing location data (12) in the underwater area and one evaluation unit or more evaluation units, and the evaluation unit or the evaluation units are arranged in such a manner that these comprise detection means (20) for detecting (14) a contact (MILEC) with the aid of the sensed location data (12) and with classification means (21) for classifying (15) the detected contact (MILEC) as a mine-like contact (MILCO) or non mine-like contact (NONMILCO), whereby classification is accomplished by comparing the contact (MILEC) with known mine information so that a mine-like contact (MILCO) can be identified as a mine contact (MINE) or as another object (NOMBO).

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.