Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

Abstract: A method of forming an optical device is provided. The method includes disposing an optical device substrate on a substrate support in a process volume of a process chamber, the optical device substrate having a first surface; and forming a first optical layer on the first surface of the optical device substrate during a first time period when the optical device substrate is on the substrate support, wherein the first optical layer comprises one or more metals in a metal-containing oxide, a metal-containing nitride, or a metal-containing oxynitride, and the first optical layer is formed without an RF-generated plasma over the optical device substrate; and forming a second optical layer with an RF-generated plasma over the first optical layer during a second time period when the optical device substrate is on the substrate support.

Abstract: Etch stop layer-based approaches for via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer, wherein each of the plurality of conductive lines has a bulk portion including a metal and has an uppermost surface including the metal and a non-metal. A hardmask layer is on the plurality of conductive lines and on an uppermost surface of the ILD layer, and includes a first hardmask component on and aligned with the uppermost surface of the plurality of conductive lines, and a second hardmask component on and aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of one of the plurality of conductive lines, the portion having a composition different than the uppermost surface including the metal and the non-metal.

Abstract: An optical device is provided. The optical device includes an optical device substrate having a first surface; and an optical device film disposed over the first surface of the optical device substrate. The optical device film is formed of titanium oxide. The titanium oxide is selected from the group of titanium(IV) oxide (TiO2), titanium monoxide (TiO), dititanium trioxide (Ti2O3), Ti3O, Ti2O, ?-TiOx, where x is 0.68 to 0.75, and TinO2n-1, where n is 3 to 9, the optical device film has a refractive index greater than 2.72 at a 520 nanometer (nm) wavelength, and a rutile phase of the titanium oxide comprises greater than 94 percent of the optical device film.

Abstract: An optical device is provided. The optical device includes an optical device substrate having a first surface; and a plurality of optical device structures disposed over the first surface of the optical device substrate, the plurality of optical device structures spaced apart from each other in a direction parallel to the first surface, and each optical device structure of the plurality of optical device structures including an optical device film. The optical device film of each optical device structure includes a first zone and a second zone, the first zone positioned between the optical device substrate and the second zone, wherein the first zone and the second zone each include one or more of oxygen and nitrogen, and the first zone and the second zone collectively include three or more metal, metalloid, or semiconductor elements.

Abstract: Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.

Abstract: An integrated circuit structure includes a first material block comprising a first block insulator layer and a first multilayer stack on the first block insulator layer, the first multilayer stack comprising interleaved pillar electrodes and insulator layers. A second material block is stacked on the first material block and comprises a second block insulator layer, and a second multilayer stack on the second block insulator layer, the second multilayer stack comprising interleaved pillar electrodes and insulator layers. At least one pillar extends through the first material block and the second material block, wherein the at least one pillar has a top width at a top of the first and second material blocks that is greater than a bottom width at a bottom of the first and second material blocks.

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

Abstract: Multifunctional molecules for selective polymer formation on conductive surfaces, and the resulting structures, are described. In an example, an integrated circuit structure includes a lower metallization layer including alternating metal lines and dielectric lines above the substrate. A molecular brush layer is on the metal lines of the lower metallization layer, the molecular brush layer including multifunctional molecules. A triblock copolymer layer is above the lower metallization layer. The triblock copolymer layer includes a first segregated block component over the dielectric lines of the lower metallization layer, and alternating second and third segregated block components on the molecular brush layer on the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.

Abstract: Embodiments described herein include a waveguide combiner having an edge coated with an optically absorbent composition and a method of coating the edge of the waveguide combiner with the optically absorbent composition. The optically absorbent composition includes one or more types of nanoparticles or microparticles, at least one of one or more dyes or one or more pigments, and a polymer matrix of one or more binders. The method includes producing an optically absorbent formulation. The optically absorbent formulation includes one or more types of particles, at least one of one or more dyes or one or more pigments, one or more binders, and one or more solvents. The optically absorbent formulation is applied on an edge of a waveguide combiner using an edge blackening tool. The formulation is cured with radiation to form the optically absorbent composition.

Abstract: Embodiments of the present disclosure generally relate to encapsulated optical devices and methods for fabricating the encapsulated optical devices. In one or more embodiments, a method for encapsulating an optical device includes depositing a metallic silver layer on a substrate, depositing a barrier layer on the metallic silver layer, where the barrier layer contains silicon nitride, a metallic element, a metal nitride, or any combination thereof, and depositing an encapsulation layer containing silicon oxide on the barrier layer.

Abstract: An optical device coating assembly is provided. The optical device coating assembly includes a substrate support operable to retain an optical device substrate. The coating assembly further includes a first actuator connected to the substrate support. The first actuator is configured to rotate the substrate support. The coating assembly includes a holder configured to hold a coating applicator against an edge of the optical device substrate when the optical device substrate is rotated on the substrate support and a second actuator operable to apply a force on the holder in a direction towards the substrate support. The second actuator is a constant force actuator.

Abstract: Embodiments of the present disclosure generally relate to imprint compositions and materials and related processes useful for nanoimprint lithography (NIL). In one or more embodiments, an imprint composition is provided and contains a plurality of passivated nanoparticles, one or more solvents, a surface ligand, an additive, and an acrylate. Each passivated nanoparticle contains a core and one or more shells, where the core contains one or more metal oxides and the shell contains one or more passivation materials. The passivation material of the shell contains one or more atomic layer deposition (ALD) materials, one or more block copolymers, or one or more silicon-containing compounds.

Abstract: The present disclosure generally relates to a method and apparatus for forming a substrate having a graduated refractive index. A method of forming a waveguide structure includes expelling plasma from an applicator having a head toward a plurality of grating structures formed on a substrate. The plasma is formed in the head at atmospheric pressure. The method further includes changing a depth of the plurality of grating structures with the plasma by removing grating material from the plurality of grating structures.

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

Abstract: Bottom-up fill dielectric materials for semiconductor structure fabrication, and methods of fabricating bottom-up fill dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a dielectric material for semiconductor structure fabrication includes forming a trench in a material layer above a substrate. A blocking layer is formed partially into the trench along upper portions of sidewalls of the trench. A dielectric layer is formed filling a bottom portion of the trench with a dielectric material up to the blocking layer. The blocking layer is removed. The forming the blocking layer, the forming the dielectric layer, and the removing the blocking layer are repeated until the trench is completely filled with the dielectric material.

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

Abstract: A method of forming a three dimensional feature inwardly of a surface of a material includes providing a droplet dispenser including an outlet configured to dispense discrete droplets of a liquid material having a reactant therein capable of reacting with, and thereby removing, portions of the material layer with which the droplets come into contact, providing a support configured support the material thereon, the support, and the droplet dispenser, movable with respect to one another, such that the outlet of the droplet dispenser is positionable over different discrete areas of the surface of the material, and positioning the surface of the material under the droplet dispenser, and dispensing droplets to discrete portions of the surface of the material in a desired area thereof, to remove at least a portion of the material in the desired area and thereby form a three dimensional recess inwardly of the surface of the material.

Abstract: Embodiments of the present disclosure generally relate to methods and materials for optical device fabrication. More specifically, embodiments described herein provide for optical film deposition methods and materials to expand the process window for amorphous optical film deposition via incorporation of dopant atoms by suppressing the crystal growth of optical materials during deposition. By enabling amorphous films to be deposited at higher temperatures, significant cost savings and increased throughput are possible.