Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack by performing a laser anneal process. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

Abstract: Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width.

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.

Abstract: A methodology for forming a compressive strain layer with increased thickness that exhibits improved device performance and the resulting device are disclosed. Embodiments may include forming a recess in a source or drain region of a substrate, implanting a high-dose impurity in a surface of the recess, and depositing a silicon-germanium (SiGe) layer in the recess.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack by performing a laser anneal process. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.

Abstract: In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.

Abstract: A methodology for forming a compressive strain layer with increased thickness that exhibits improved device performance and the resulting device are disclosed. Embodiments may include forming a recess in a source or drain region of a substrate, implanting a high-dose impurity in a surface of the recess, and depositing a silicon-germanium (SiGe) layer in the recess.

Abstract: The present disclosure provides an improved method for forming a thin semiconductor alloy layer on top of a semiconductor layer. The proposed method relies on an implantation of appropriate impurity species before performing deposition of the semiconductor alloy film. The implanted species cause the semiconductor alloy layer to be less unstable to wet and dry etches performed on the device surface after deposition. Thus, the thickness uniformity of the semiconductor alloy film may be substantially increased if the film is deposited after performing the implantation. On the other hand, some implanted impurities have been found to decrease the growth rate of the semiconductor alloy layer. Thus, by selectively implanting appropriate impurities in predetermined portions of a wafer, a single deposition step may be used in order to form a semiconductor alloy layer with a thickness which may be locally adjusted at will.

Abstract: A method for fabricating an integrated circuit includes providing a silicon semiconductor substrate including a single-crystal crystallography, removing a portion of the semiconductor substrate to form a fin structure, the fin structure being defined by adjacent trenches formed within the semiconductor substrate, and forming an insulating material in the trenches, the insulating material covering a first portion of the fin and leaving a second portion of the fin exposed. The method further includes applying a wet etchant to the second portion of the fin, the wet etchant including an etching chemistry that selectively etches the fin against a <111> crystallographic orientation of the single-crystal silicon.

Abstract: An illustrative semiconductor device disclosed herein includes a semiconductor substrate. The semiconductor substrate includes a first semiconductor material. In the first semiconductor material, a recess is provided. The recess is filled with a second semiconductor material having a different composition than the first semiconductor material. The semiconductor device further includes a first transistor including a source region, a drain region, a gate electrode and a channel region below the gate electrode. The channel region is arranged at two or more laterally opposite sides of the drain region. The source region is arranged at two or more laterally opposite sides of the channel region. The drain region includes a low doped drift region and a highly doped region. A dopant concentration in the low doped drift region is at least one of smaller than a dopant concentration in the highly doped region and approximately zero. At least the low doped drift region is provided in the second semiconductor material.

Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer.

Abstract: A method for fabricating an integrated circuit includes forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, forming a sacrificial spacer on sidewalls of the first and second gate electrode structures, and forming deep drain and source regions selectively in the first and second active regions by using the sacrificial spacer as an implantation mask. The method further includes forming drain and source extension and halo regions in the first and second active regions after removal of the sacrificial spacer and forming a fluorine implant region in the halo region of the first active region before or after formation of the drain and source extension and halo regions.

Abstract: Methods and apparatus are provided for an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator.

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Abstract: In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.

Abstract: The present disclosure provides an improved method for forming a thin semiconductor alloy layer on top of a semiconductor layer. The proposed method relies on an implantation of appropriate impurity species before performing deposition of the semiconductor alloy film. The implanted species cause the semiconductor alloy layer to be less unstable to wet and dry etches performed on the device surface after deposition. Thus, the thickness uniformity of the semiconductor alloy film may be substantially increased if the film is deposited after performing the implantation. On the other hand, some implanted impurities have been found to decrease the growth rate of the semiconductor alloy layer. Thus, by selectively implanting appropriate impurities in predetermined portions of a wafer, a single deposition step may be used in order to form a semiconductor alloy layer with a thickness which may be locally adjusted at will.

Abstract: A method for fabricating an integrated circuit includes forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, forming a sacrificial spacer on sidewalls of the first and second gate electrode structures, and forming deep drain and source regions selectively in the first and second active regions by using the sacrificial spacer as an implantation mask. The method further includes forming drain and source extension and halo regions in the first and second active regions after removal of the sacrificial spacer and forming a nitrogen implant region in the halo region of the first active region after formation of the drain and source extension and halo regions.

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.