Abstract: Silicon carbide devices and methods of fabricating silicon carbide devices are provided by forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate. At least one first region of n-type silicon carbide is formed extending through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer. At least one second region of n-type silicon carbide is also formed adjacent and spaced apart from the first region of n-type silicon carbide. A gate dielectric is formed-over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide. A gate contact is formed on the gate dielectric. A first contact is also formed so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide. A second contact is also formed on the substrate.

Abstract: The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second metal gate electrode material having a work function compatible with the second transistor and the first metal gate electrode material is also located over the second metal gate electrode material, which forms a gate stack.

Abstract: The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second metal gate electrode material having a work function compatible with the second transistor and the first metal gate electrode material is also located over the second metal gate electrode material, which forms a gate stack.

Abstract: Edge termination for a silicon carbide Schottky rectifier is provided by including a silicon carbide epitaxial region on a voltage blocking layer of the Schottky rectifier and adjacent a Schottky contact of the silicon carbide Schottky rectifier. The silicon carbide epitaxial layer may have a thickness and a doping level so as to provide a charge in the silicon carbide epitaxial region based on the surface doping of the blocking layer. The silicon carbide epitaxial region may form a non-ohmic contact with the Schottky contact. The silicon carbide epitaxial region may have a width of from about 1.5 to about 5 times the thickness of the blocking layer. Schottky rectifiers with such edge termination and methods of fabricating such edge termination and such rectifiers are also provided. Such methods may also advantageously improve the performance of the resulting devices and may simplify the fabrication process.

Abstract: A bipolar device has at least one p-type layer of single crystal silicon carbide and at least one n-type layer of single crystal silicon carbide, wherein those portions of those stacking faults that grow under forward operation are segregated from at least one of the interfaces between the active region and the remainder of the device.

Abstract: The present invention provides a bipolar transistor for use in increasing a speed of a flash memory cell having a source region and a drain region and first and second complementary tubs. In one embodiment, a base for the bipolar transistor is located in the first complementary tub. The first complementary tub functions as a collector for the bipolar transistor. The bipolar transistor base also uniquely functions as the source region. The bipolar transistor's emitter is also located in the first complementary tub and proximate the base. For example, the emitter may be located adjacent the base or actually located in the base. In an additional embodiment, the opposing bases and emitters are located on opposing sides of and proximate to the flash memory cell.

Abstract: The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.

Abstract: Edge termination for a silicon carbide Schottky rectifier is provided by including a silicon carbide epitaxial region on a voltage blocking layer of the Schottky rectifier and adjacent a Schottky contact of the silicon carbide Schottky rectifier. The silicon carbide epitaxial layer may have a thickness and a doping level so as to provide a charge in the silicon carbide epitaxial region based on the surface doping of the blocking layer. The silicon carbide epitaxial region may form a non-ohmic contact with the Schottky contact. The silicon carbide epitaxial region may have a width of from about 1.5 to about 5 times the thickness of the blocking layer. Schottky rectifiers with such edge termination and methods of fabricating such edge termination and such rectifiers are also provided. Such methods may also advantageously improve the performance of the resulting devices and may simplify the fabrication process.

Abstract: The present invention provides a semiconductor device that comprises a tub region located in a semiconductor substrate, wherein the tub region has a tub electrical contact connected thereto. The semiconductor device further comprises a trap charge insulator layer located on the first insulator layer and a control gate located over the trap charge insulator layer. The control gate has a gate contact connected thereto for providing a second bias voltage to the semiconductor device that, during programming, is opposite in polarity to that of the first bias voltage.

Abstract: A memory cell of a non-volatile memory includes a control gate oxide layer having graded portions with greatly reduced stress on a polysilicon floating gate layer. The method of making the control gate oxide layer preferably includes growing a first oxide portion by upwardly ramping the polysilicon floating gate layer to a first temperature lower than a glass transition temperature, and exposing the polysilicon floating gate layer to an oxidizing ambient at the first temperature and for a first time period. Also, the method includes growing a second oxide portion between the first oxide portion and the polysilicon floating gate layer by exposing the polysilicon floating gate layer to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period. The second oxide portion may have a thickness in a range of about 25 to 75% of a total thickness of the graded, grown, control gate oxide layer.

Abstract: A non-volatile memory cell and associated cell array and memory device having reduced program disturb, improved retention of programmed information, and reduced power consumption are disclosed. The memory cell includes a control device coupled to a switch device via a common floating gate, with the control device and the switch device formed on a common substrate, and the switch device formed at least in part in a tub region on the substrate. The tub region has a contact region formed therein. The contact region is adapted for application of a bias voltage to the tub region during a programming operation of the memory cell so as to reduce a programming voltage required to program the memory cell. In an illustrative embodiment, a drain-to-substrate voltage required to program the memory cell is reduced from a conventional value of about 6.5 volts to a value of about 3.5 volts, thus alleviating program disturb problems that can result, e.g.

Abstract: A method for electromagnetically shielding circuits which combine to form an integrated circuit device provides isolated silicon islands surrounded laterally and subjacently by conductive material. The isolated silicon islands may be covered individually or as a group by a conductive cover. The integrated circuit may include at least one silicon island including an analog circuit and at least one silicon island including a digital circuit, the analog and digital circuits electromagnetically shielded from one another. The method for forming the structure includes providing a first semiconductor substrate and hydrophilically bonding a substructure to the first semiconductor substrate. The substructure includes the isolated silicon islands surrounded by the conductive material. The substructure may be formed on a second semiconductor substrate by implanting an impurity region into an upper portion of the second semiconductor substrate.

Abstract: A memory cell of a non-volatile memory includes a tunnel oxide layer having graded portions with greatly reduced stress on a silicon substrate. The method of making the tunnel oxide preferably includes growing a first oxide portion by upwardly ramping the silicon substrate to a first temperature lower than a glass transition temperature, and exposing the silicon substrate to an oxidizing ambient at the first temperature and for a first time period. Also, the method includes growing a second oxide portion between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period. The second oxide portion may have a thickness in a range of about 2 to 50% of a total thickness of the graded, grown, tunnel oxide layer.

Abstract: Organophosphines of the formula (R)aP(H)3−a( where R is C1-C20 alkyl, alkenyl, alkaryl or styryl and a is 1, 2, or 3) are produced by (i) reacting a tris(hydroxyorgano)phosphine (THP) with an organic halogen containing compound; (ii) reacting the product of (i) with a base; (iii) removing aldehydes from the product of (ii) and adding an organic phase, followed by distillation or phase-separation to obtain the desired product.

Abstract: Silicon carbide devices and methods of fabricating silicon carbide devices are provided by forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate. At least one first region of n-type silicon carbide is formed extending through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer. At least one second region of n-type silicon carbide is also formed adjacent and spaced apart from the first region of n-type silicon carbide. A gate dielectric is formed-over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide. A gate contact is formed on the gate dielectric. A first contact is also formed so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide. A second contact is also formed on the substrate.

Abstract: A non-volatile memory device is disclosed which includes an erase device that is shared among an array of memory cells. Each of the memory cells in the array includes a control device coupled to a switch device via a common floating gate. Each of at least a subset of the memory cells further includes a portion of the shared erase device, the portion of the shared erase device associated with a given one of the memory cells being coupled to the switch device of that cell via the floating gate of that cell. The shared erase device is utilizable in performing an erase operation for each of the memory cells associated therewith. Advantageously, the use of the shared erase device substantially reduces the circuit area requirements of the memory array. The invention is particularly well suited for implementation in single-poly flash EEPROM embedded memory devices in integrated circuit applications.

Abstract: Silicon carbide devices and methods of fabricating silicon carbide devices are provided by forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate. At least one first region of n-type silicon carbide is formed extending through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer. At least one second region of n-type silicon carbide is also formed adjacent and spaced apart from the first region of n-type silicon carbide. A gate dielectric is formed over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide. A gate contact is formed on the gate dielectric. A first contact is also formed so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide. A second contact is also formed on the substrate.

Abstract: The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second metal gate electrode material having a work function compatible with the second transistor and the first metal gate electrode material is also located over the second metal gate electrode material, which forms a gate stack.

Abstract: A bipolar transistor includes an oxide layer having graded portions with greatly reduced stress on a silicon substrate. The method of making the oxide preferably includes growing a first oxide portion by upwardly ramping the silicon substrate to a first temperature lower than a glass transition temperature, and exposing the silicon substrate to an oxidizing ambient at the first temperature and for a first time period. Also, the method includes growing a second oxide portion between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period. The second oxide portion may have a thickness in a range of about 2 to 75% of a total thickness of the graded, grown, oxide layer. The step of upwardly ramping preferably includes upwardly ramping the temperature at a relatively high ramping rate to reduce any oxide formed during the upward ramping.

Abstract: The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second metal gate electrode material having a work function compatible with the second transistor and the first metal gate electrode material is also located over the second metal gate electrode material, which forms a gate stack.