Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Abstract: An electrical transmission line repair device including a first conductor clamp, a second conductor clamp and at least one tie rail extending between the first and second conductor clamps in a spaced apart orientation. The first conductor clamp including a lower assembly and an upper assembly. The lower assembly and the upper assembly are slidably engageable with each other so as to define a conductor cavity extending therealong. Clamping fasteners are configured to extend through openings in the upper assembly so as to be threadable toward and away from the conductor contact region of the lower assembly within the conductor cavity.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

Abstract: A torque limiting fastener comprising a body. The body includes a threadform, an inner bore and a controlled break region. The body defines an elongated body extending from a first end to a second end, and the body includes an outer surface. The threadform extends at least partially between the first end and the second end along the outer surface. The inner bore extends from the second end at least partially toward the first end of the body. The controlled break region is positioned between the inner bore and the outer surface. The controlled break region includes an outer surface break point formed into the outer surface and an inner surface break point formed into the inner bore. The outer surface break point and the inner surface break point defining a shear plane therebetween.

Abstract: Chip structures that include distributed wiring layouts and fabrication methods for forming such chip structures. A device structure is formed that includes a plurality of first device regions and a plurality of second device regions. A first wiring level is formed that includes a first wire coupled with the first device regions. A second wiring level is formed that includes a second wire coupled with the second device regions. The first wiring level is vertically separated from the second wiring level by a buried oxide layer of the silicon-on-insulator substrate.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Abstract: A tangent suspension bracket configured for coupling to at least one of a suspension insulator and a conductor clamp assembly. The tangent suspension bracket further includes a central cap, a first end attachment structure and a second end attachment structure. The central cap structure includes an upper wall having an opening and a depending skirt, together defining a downwardly opening cavity. The opening is structurally configured to allow the passage of a portion of one of the suspension insulator and the conductor clamp assembly while maintaining a portion within the downwardly opening cavity, so as to secure the central cap structure to one of the suspension insulator and the conductor clamp assembly. The first end attachment assembly extends from the central cap and the second end attachment structure extends from the central cap in the opposite direction.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Abstract: An electrical transmission line repair device including a first conductor clamp, a second conductor clamp and at least one tie rail extending between the first and second conductor clamps in a spaced apart orientation. The first conductor clamp including a lower assembly and an upper assembly. The lower assembly and the upper assembly are slidably engageable with each other so as to define a conductor cavity extending therealong. Clamping fasteners are configured to extend through openings in the upper assembly so as to be threadable toward and away from the conductor contact region of the lower assembly within the conductor cavity.

Abstract: An approach for sinking heat from a transistor is provided. A method includes forming a substrate contact extending from a first portion of a silicon-on-insulator (SOI) island to a substrate. The method also includes forming a transistor in a second portion of the SOI island. The method further includes electrically isolating the substrate contact from the transistor by doping the first portion of the SOI island.

Abstract: Approaches for body contacted transistors are provided. A method of manufacturing a semiconductor structure includes forming a field effect transistor (FET) including a channel and a gate. The method also includes forming a diode that is electrically connected between the channel and the gate, wherein the diode and channel are contained in a same layer of material.

Abstract: Embodiments of the present invention provide a circuit and method to characterize the impact of bias temperature instability on semiconductor devices. The circuit comprises a transistor having a gate, drain, source, and body terminal. Two AC pad sets each having a plurality of conductive pads. Two DC pads are in communication with a DC supply and/or meter. The gate terminal is in communication with a first conductive pad included in the plurality of conductive pads of each of the AC pad sets. The drain terminal is in communication with a second conductive pad of an AC pad set and the source terminal with a second conductive pad of another AC pad set. One DC pad is in communication with the gate terminal through a first serial resistor and another DC pad with the body terminal through a second serial resistor and provides an open-circuit for the gate and body terminals.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer.

Abstract: A torque limiting fastener comprising a body. The body includes a threadform, an inner bore and a controlled break region. The body defines an elongated body extending from a first end to a second end, and the body includes an outer surface. The threadform extends at least partially between the first end and the second end along the outer surface. The inner bore extends from the second end at least partially toward the first end of the body. The controlled break region is positioned between the inner bore and the outer surface. The controlled break region includes an outer surface break point formed into the outer surface and an inner surface break point formed into the inner bore. The outer surface break point and the inner surface break point defining a shear plane therebetween.

Abstract: A fastener for a connector in an electrical coupling including a threaded bolt, a keeper member and a biasing member. The keeper member having a base and a distal member spaced apart from each other and a collapsible portion coupling the base and the distal member to each other in electrical communication. The second end of the threaded bolt extends to the base and is in electrical communication therewith. The distal member has a conductor contact surface. The biasing member includes an inner washer, an outer washer, and a Belleville washer positioned therebetween. The biasing member is insertable between the base and the distal member so that the inner washer is positioned between the base and the Belleville washer and the outer washer is positioned between the Belleville washer and the distal member. The collapsible portion provides an electrical shunt around the biasing member.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer.