Patents by Inventor Ren Wang

Ren Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HIGH ELECTRON MOBILITY TRANSISTOR AND FABRICATION METHOD THEREOF
    Publication number: 20230020271
    Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 19, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
  • SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    Publication number: 20230014253
    Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.
    Type: Application
    Filed: August 2, 2021
    Publication date: January 19, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shi-You Liu, Shih-Cheng Chen, Chia-Wei Chang, Chia-Ming Kuo, Tsai-Yu Wen, Yu-Ren Wang
  • High electron mobility transistor and fabrication method thereof
    Patent number: 11557666
    Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.
    Type: Grant
    Filed: November 22, 2020
    Date of Patent: January 17, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
  • ELECTRIC VALVE
    Publication number: 20230010390
    Abstract: An electric valve, comprising a housing and an end cover. A cavity and a valve port are formed in the housing. The electric valve further comprises a rotor assembly, a rod assembly, and a valve core assembly; the rotor assembly is connected to one end of the rod assembly; and the other end of the rod assembly is connected to the valve core assembly. The electric valve further comprises a sealing component, and the sealing component is distant from the valve port with respect to the valve core assembly; the sealing component comprises a first cylindrical portion, a membrane portion, and an annular sealing portion; by providing the sealing component, the first cylindrical portion is connected to the rod assembly and a connection position is sealed.
    Type: Application
    Filed: December 8, 2020
    Publication date: January 12, 2023
    Applicant: ZHEJIANG SANHUA AUTOMOTIVE COMPONENTS CO., LTD.
    Inventors: Ren Wang, Lixin Wang
  • Efficient way to perform location SLO validation
    Patent number: 11552861
    Abstract: A method, apparatus, and system for performing a Location SLO check based on a location scatter table is disclosed. A location scatter table is maintained, the location scatter table indicative of updated geographical location distribution of all backups of all assets. A Location Service Level Objective (SLO) associated with a first asset is determined, the Location SLO associated with the first asset specifying one or more allowed locations where backups of the first asset are permitted to be located. All locations where at least one backup of the first asset is located are determined. A Location SLO check for the first asset is performed, wherein the Location SLO check passes when all the locations where at least one backup of the first asset is located fall within the allowed locations specified by the Location SLO.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: January 10, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Ren Wang, Scott Quesnelle, Mengze Liao
  • Leak-proof lost-circulation control water-based drilling fluid composition and preparation method and use thereof
    Patent number: 11542425
    Abstract: The present disclosure a leak-proof lost-circulation control water-based drilling fluid composition and preparation method and use thereof.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: January 3, 2023
    Assignee: Southwest Petroleum University
    Inventors: Yang Bai, Lingfeng Wu, Jing Zhang, Wenzhe Li, Pingya Luo, Feng Dai, Jingping Liu, Ren Wang, Daoxiong Li, Wen Xu
  • Semiconductor device and method
    Patent number: 11545546
    Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
  • Semiconductor device and fabrication method thereof
    Patent number: 11545557
    Abstract: A semiconductor device includes substrate having a fin structure thereon, a gate structure overlying the fin structure, a polymer block at a corner between the gate structure and the fin structure, and a source/drain region on the fin structure. The polymer block includes a nitridation layer in proximity to a sidewall of the gate structure.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: January 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wei Chang, Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Shao-Wei Wang, Yu-Ren Wang, Chia-Yuan Chang
  • HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME
    Publication number: 20220416068
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Interconnect structures for semiconductor devices and methods of manufacturing the same
    Patent number: 11532712
    Abstract: A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Lien Huang, Ching-Feng Fu, Guan-Ren Wang, Che-Ming Hsu
  • Semiconductor device and method for fabricating the same
    Patent number: 11527448
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: December 13, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Methods for patterning a silicon oxide-silicon nitride-silicon oxide stack and structures formed by the same
    Patent number: 11521846
    Abstract: A layer stack is formed over a conductive material portion located on a substrate. The layer stack contains a first silicon oxide layer, a silicon nitride layer formed by chemical vapor deposition, and a second silicon oxide layer. A patterned etch mask layer including an opening is formed over the layer stack. A via cavity extending through the layer stack and down to the conductive material portion is formed by isotropically etching portions of the layer stack underlying the opening in the patterned etch mask layer using an isotropic etch process. A buffered oxide etch process may be used, in which the etch rate of the silicon nitride layer is less than, but is significant enough, compared to the etch rate of the first silicon oxide layer to provide tapered straight sidewalls on the silicon nitride layer. An optical device including a patterned layer stack can be provided.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Ren Wang, Yuan-Chih Hsieh
  • Semiconductor device and method
    Patent number: 11515165
    Abstract: In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
  • Processor and method implementing a cacheline demote machine instruction
    Patent number: 11513957
    Abstract: Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Ren Wang, Andrew J. Herdrich, Yen-cheng Liu, Herbert H. Hum, Jong Soo Park, Christopher J. Hughes, Namakkal N. Venkatesan, Adrian C. Moga, Aamer Jaleel, Zeshan A. Chishti, Mesut A. Ergin, Jr-shian Tsai, Alexander W. Min, Tsung-yuan C. Tai, Christian Maciocco, Rajesh Sankaran
  • Display system
    Patent number: 11508293
    Abstract: A display system includes a display panel that includes a plurality of micro-light-emitting diodes (microLEDs), the display panel being divided into a plurality of display blocks; and a plurality of drivers correspondingly driving the plurality of display blocks. Data signals of each driver are provided to a corresponding display block at different times within a horizontal scan period.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: November 22, 2022
    Assignee: Prilit Optronics, Inc.
    Inventors: Biing-Seng Wu, Tzung-Ren Wang
  • Semiconductor device with strain relaxed layer
    Patent number: 11508818
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: November 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Semiconductor Device and Method
    Publication number: 20220367198
    Abstract: In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
  • Methods and systems for searching directory access groups
    Patent number: 11500873
    Abstract: Methods and systems for searching directory access groups are disclosed. A set of groups associated with a logon user is determined. The set of groups is partitioned into one or more disjoint subsets, wherein each of the disjoint subsets is represented by a data representation including a root node and one or more intermediate nodes. For each of the disjoint subsets, the disjoint subset is path compressed to flatten a structure of the data representation representing the disjoint subset. The data representation is cached to a database cache.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: November 15, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Frank Huang, Cherami Liu, Aaron Ren Wang, Hanson Wang
  • Techniques for dynamic database access modes
    Patent number: 11500825
    Abstract: Techniques and apparatus for dynamic data access mode processes are described. In one embodiment, for example, an apparatus may a processor, at least one memory coupled to the processor, the at least one memory comprising an indication of a database and instructions, the instructions, when executed by the processor, to cause the processor to determine a database utilization value for a database, perform a comparison of the database utilization value to at least one utilization threshold, and set an active data access mode to one of a low-utilization data access mode or a high-utilization data access mode based on the comparison. Other embodiments are described.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: November 15, 2022
    Assignee: INTEL CORPORATION
    Inventors: Ren Wang, Bruce Richardson, Tsung-Yuan Tai, Yipeng Wang, Pablo De Lara Guarch
  • Semiconductor Device and Method
    Publication number: 20220359745
    Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu