Abstract: In some embodiments, the present disclosure relates to a piezomicroelectromechanical system (piezoMEMS) device that includes a second piezoelectric layer arranged over the first electrode layer. A second electrode layer is arranged over the second piezoelectric layer. A first contact is arranged over and extends through the second electrode layer and the second piezoelectric layer to contact the first electrode layer. A dielectric liner layer is arranged directly between the first contact and inner sidewalls of the second electrode layer and the second piezoelectric layer. A second contact is arranged over and electrically coupled to the second electrode layer, wherein the second contact is electrically isolated from the first contact.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.

Abstract: A method for producing a cold-water-soluble starch. The method includes: 1) adding a starch and 3-45 wt. % of an ethanol aqueous solution to a container, and stirring a mixture of the starch and the ethanol aqueous solution in the container, thus yielding a starch-ethanol-water; 2) introducing the starch-ethanol-water to an extruder and producing a noodle extrudate, where the extruder comprises 3 continuous temperature control areas: a first area having a temperature of 50° C., a second area having a temperature of between 95 and 120° C., and a third area having a temperature of 60° C.; a rotation speed of the extruder is 70-150 rpm; and the noodle extrudate has a diameter of 0.2-0.5 cm; 3) pressing and roll slitting the noodle extrudate, thus yielding a plurality of slices; and 4) drying the plurality of slices in a microwave vacuum oven, cooling, and pulverizing the plurality of slices.

Abstract: A semiconductor device includes a first conductive feature, a first dielectric layer over the first conductive feature, a second conductive feature extending through the first dielectric layer, an air gap between the first dielectric layer and the second conductive feature, and an etch stop layer over the second conductive feature and the first dielectric layer. The etch stop layer covers the air gap, and the air gap extends above a bottommost surface of the etch stop layer.

Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product for grouping objects in a data management system. The method includes: detecting operation parameters of at least two of a plurality of objects in a data management system, and determining a rate of correlation between the at least two objects based on the detected operation parameters, wherein the rate of correlation indicates a degree of correlation between the at least two objects. The method further includes: comparing the determined rate of correlation with a predetermined threshold, and determining, based on the comparison of the determined rate of correlation with the predetermined threshold, grouping of the at least two objects. With this method, objects with a high degree of correlation are logically grouped together, so that a user can manage objects in batches in an efficient manner during object management, thus improving the system performance.

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

Abstract: A pulse-width modulation (PWM) circuit includes a partition circuit coupled to receive a PWM value representing a duty cycle of a PWM signal to be generated, and configured to accordingly generate a most-significant-bits (MSB) value representing higher-order bits of the PWM value and a least-significant-bits (LSB) value representing lower-order bits of the PWM value; a PWM generator coupled to receive the MSB value or a derivative thereof, and configured to accordingly generate a primary signal with a duty cycle corresponding to the MSB value; a delay circuit that generates a delay signal representing the primary signal with delay time determined according to the LSB value or a derivative thereof; and a combine circuit that generates the PWM signal according to the primary signal and the delay signal, by performing a logical operation on the primary signal and the delay signal.

Abstract: A three-dimensional printing device including a rigid optically transparent plate, a release film, an adhesive layer, a light source, and a reflection assembly is provided. The rigid optically transparent plate has a first surface and a second surface opposite the first surface, the release film is disposed on a side of the rigid optically transparent plate adjacent to the first surface, and the adhesive layer is arranged between the rigid optically transparent plate and the release film. The light source is disposed on a side of the rigid optically transparent plate adjacent to the second surface, and the reflection assembly includes at least one mirror and is arranged at a position capable of forming a light path from the light source to the rigid optically transparent plate.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a microelectromechanical systems (MEMS) structure overlying a substrate. A capping structure overlies the MEMS structure. The capping structure at least partially defines a cavity. The MEMS structure is disposed in the cavity. An outgas structure adjacent to the cavity. The outgas structure comprises an amorphous material.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes separating an interlayer dielectric (ILD) into a plurality of portions. The plurality of portions of ILD, separated from each other along a first lateral direction and a second lateral direction, overlay a plurality of groups of epitaxial regions, respectively. The method includes performing an etching process to expose the plurality of groups of epitaxial regions, wherein the etching process comprises a plurality of stages, each of the stages comprising a respective etchant. The method includes forming a plurality of conductive contacts electrically coupled to the plurality of epitaxial regions, respectively.

Abstract: Technologies for dynamically managing a batch size of packets include a network device. The network device is to receive, into a queue, packets from a remote node to be processed by the network device, determine a throughput provided by the network device while the packets are processed, determine whether the determined throughput satisfies a predefined condition, and adjust a batch size of packets in response to a determination that the determined throughput satisfies a predefined condition. The batch size is indicative of a threshold number of queued packets required to be present in the queue before the queued packets in the queue can be processed by the network device.

Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product that involve exporting a log. The method includes acquiring a first set of attributes indicating a target asset among assets protected by a data protection product, a second set of attributes indicating target tasks executed on the target asset, and a third set of attributes indicating a computing resource running the data protection product. The method further includes determining an export time consumed to export a log of the target asset based on the first set of attributes, the second set of attributes, and the third set of attributes. With the embodiments of the present disclosure, the time required for exporting a log can be accurately estimated while the log is exported.

Abstract: The present invention relates to platform power management.

Abstract: The present disclosure relates to a method, an electronic device, and a computer program product for recovering data. For example, a method for recovering data is provided. The method may comprise acquiring metadata corresponding to to-be-recovered target data, the metadata comprising at least a first part of metadata corresponding to a first set of data blocks and a second part of metadata corresponding to a second set of data blocks. The method may further comprise acquiring, based on the first part of metadata, the first set of data blocks from a first backup storage device in a plurality of backup storage devices that store the target data. The method may further comprise acquiring, based on the second part of metadata, the second set of data blocks from a second backup storage device in the plurality of backup storage devices. In addition, the method may further comprise recovering the target data based on at least the first set of data blocks and the second set of data blocks.

Abstract: A method for extending shelf life of germ remained rice includes evenly spreading the germ remained rice on a sheet tray, and moderately moistening the germ remained rice, packing the germ remained rice moistened, and irradiating the germ remained rice with an electron beam.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.