Abstract: Methods, systems, and devices for status check using signaling are described. A memory system may receive ready signals from memory dies. The ready signal may indicate whether a memory die is available to receive a command. The memory system may generate an indicator of whether the memory die is available based on values of ready signals. The memory system may output the indicator to a controller over one or more pins based on generating the indicator.

Abstract: Systems, apparatuses, and methods related to configurable media structure are described. A memory device can be configured to boot up in a variety of configurations. The variety of configurations can include using the memory device for persistent memory storage, for non-persistent memory storage, etc. For instance, an apparatus can include a first memory array and a second memory array. The apparatus can include a memory controller coupled to the first memory array and the second memory array. The second memory array can be configured to store at least two boot images. The first memory array can be configured to operate based on which of the at least two boot images is used.

Abstract: A method is described that includes receiving a write request with user data and a logical address and select a next address queue from a plurality of next address queues based on a reciprocal relationship between short-term usage information associated with the logical address and a set of characteristics of the selected next address queue. Each next address queue in the plurality of next address queues stores physical addresses that are designated to be used for fulfilling write requests. Further, a next physical address is removed from the selected next address queue and the user data of the write request is written to the next physical address in a memory device.

Abstract: A method includes writing a first codeword to a first set of contiguous partitions in a first memory die of a memory device. The method further includes writing a first portion of a second codeword to a second set of contiguous partitions in the first memory die of the memory device and writing a second portion of the second codeword to a first set of contiguous partitions in a second memory die of the memory device. The method also includes writing a third codewords to a second set of contiguous partitions in the second memory die of the memory device.

Abstract: Methods and systems associated with data modification are described. Examples can include receiving, at a controller of a device, data associated with a read or write command transmitted to a memory resource and modifying the data using logic before transmitting the data to a host or image sensor or before writing the data to the memory resource. The modification can include removing one or more bits from the data, reordering one or more bits of the data, changing a format of the data, or any combination thereof. The modified data can be transmitted to the host or image sensor or written to the memory resource. In some examples, a plurality of memory devices can combine modified data for transmitting to a host.

Abstract: Systems, apparatuses, and methods related to configurable media structure are described. A memory device can be configured to boot up in a variety of configurations. The variety of configurations can include using the memory device for persistent memory storage, for non-persistent memory storage, etc. For instance, an apparatus can include a first memory array and a second memory array. The apparatus can include a memory controller coupled to the first memory array and the second memory array. The second memory array can be configured to store at least two boot images. The first memory array can be configured to operate based on which of the at least two boot images is used.

Abstract: Systems, apparatuses, and methods related to predictive memory management are described. Error correction operations can be performed on a memory system and can include a latency associated with performing various error correction techniques on data and the health of physical addresses used to store the data can be predicted based on that latency information. In an example, a method can include determining, by a controller, latency information corresponding to one or more error correction operations performed on data received by the controller, and assigning, based on the latency information corresponding to a health of physical address locations corresponding to the data, and taking an action involving the physical address locations based, at least in part, on the information corresponding to the health of the plurality of physical address locations corresponding to the data.

Abstract: Systems, apparatuses, and methods related log compression are described. In an example, a system log that identifies targeted data may be compiled in a memory resource during an execution of an operation using that memory resource. The system log may be analyzed utilizing a portion of the memory resource that would otherwise be available to be utilized in the execution of the operation. The system log may be compressed during the execution of the operation, the level or timing of such compression may be based on the analysis that occurs contemporaneous to or as a result of executing the operation. In some examples, compressing the system log may include discarding a portion of the system log. Compressing the system log may also include extracting the targeted data from the system log as the system log is being compiled and converting the extracted targeted data to structured data.

Abstract: Systems, apparatuses, and methods related to predictive memory management are described. Error correction operations can be performed on a memory system and can include a latency associated with performing various error correction techniques on data and the health of physical addresses used to store the data can be predicted based on that latency information. In an example, a method can include determining, by a controller, latency information corresponding to one or more error correction operations performed on data received by the controller, and assigning, based on the latency information corresponding to a health of physical address locations corresponding to the data, and taking an action involving the physical address locations based, at least in part, on the information corresponding to the health of the plurality of physical address locations corresponding to the data.

Abstract: Systems, apparatuses, and methods related to thermal leveling are described. Thermal leveling can be performed on a host computing system as opposed to on a memory system. Thermal leveling can include operations performed by a host to control temperature characteristics and/or power consumption of a memory system. For instance, a host computing system can control temperature characteristics of multiple memory devices that are deployed in a memory system. In an example, a set of processing resources (e.g., a thermal leveling component) can be provided on a host. The set of processing resources can receive information corresponding to thermal characteristics of a memory device coupled to the host and control a thermal setting for the memory device based on the received thermal characteristics.

Abstract: A method is described that includes receiving a write request with user data and a logical address and select a next address queue from a plurality of next address queues based on a reciprocal relationship between short-term usage information associated with the logical address and a set of characteristics of the selected next address queue. Each next address queue in the plurality of next address queues stores physical addresses that are designated to be used for fulfilling write requests. Further, a next physical address is removed from the selected next address queue and the user data of the write request is written to the next physical address in a memory device.

Abstract: Systems, apparatuses, and methods related to thermal leveling are described. Thermal leveling can be performed on a host computing system as opposed to on a memory system. Thermal leveling can include operations performed by a host to control temperature characteristics and/or power consumption of a memory system. For instance, a host computing system can control temperature characteristics of multiple memory devices that are deployed in a memory system. In an example, a set of processing resources (e.g., a thermal leveling component) can be provided on a host. The set of processing resources can receive information corresponding to thermal characteristics of a memory device coupled to the host and control a thermal setting for the memory device based on the received thermal characteristics.

Abstract: Generally, a computing system includes processing circuitry, such as one or more processors or other suitable components, and memory devices, such as chips or integrated circuits. The memory devices may be associated with thermal limits. Saving data in such a way that causes a thermal limit of the memory device to be exceeded may cause loss of stored data and/or device over-heating. As discussed herein, a memory controller associated with the processing circuitry may determine whether a thermal limit is expected to be exceeded for a current memory writing operation. When the thermal limit is expected to be exceeded, the memory controller may respond by modifying the memory operation in such a manner that the thermal limit is not exceeded, thereby improving operation of at least the memory device and/or memory controller.

Abstract: Systems, apparatuses, and methods related to predictive memory management are described. Error correction operations can be performed on a memory system and can include a latency associated with performing various error correction techniques on data and the health of physical addresses used to store the data can be predicted based on that latency information. In an example, a method can include determining, by a controller, latency information corresponding to one or more error correction operations performed on data received by the controller, and assigning, based on the latency information corresponding to a health of physical address locations corresponding to the data, and taking an action involving the physical address locations based, at least in part, on the information corresponding to the health of the plurality of physical address locations corresponding to the data.

Abstract: Systems, apparatuses, and methods related to configurable media structure are described. A memory device can be configured to boot up in a variety of configurations. The variety of configurations can include using the memory device for persistent memory storage, for non-persistent memory storage, etc. For instance, an apparatus can include a first memory array and a second memory array. The apparatus can include a memory controller coupled to the first memory array and the second memory array. The second memory array can be configured to store at least two boot images. The first memory array can be configured to operate based on which of the at least two boot images is used.

Abstract: Systems, apparatuses, and methods related to host-based error correction are described. Error correction operations can be performed on a host computing system as opposed to on a memory system. For instance, data containing erroneous bits can be transferred from a memory system to a host computing system and error correction operations can be performed using circuitry resident on the host computing system. In an example, a method can include receiving, by a host computing system, data that comprises a plurality of uncorrected bits from a memory system coupleable to the host computing system, determining an acceptable error range for the data based at least in part on an application associated with the data, and performing, using error correction logic resident on the host computing system, an initial error correction operation on the data based at least in part on the acceptable error range.

Abstract: Systems, apparatuses, and methods related to channel architecture for memory devices are described. Various applications can access data from a memory device via a plurality of channels. The channels can be selectively enabled or disabled based on the behavior of the applications. For instance, an apparatus in the form of a memory system can include an interface coupled to a controller and a plurality of channels. The controller can be configured to determine an aggregate amount of bandwidth used by a plurality of applications accessing data from a memory device coupled to the controller via the plurality of channels and disable one or more channels of the plurality of channels based, at least in part, on the aggregate amount of bandwidth used by the plurality of applications.

Abstract: Generally, a computing system includes processing circuitry, such as one or more processors or other suitable components, and memory devices, such as chips or integrated circuits. The memory devices may be associated with thermal limits. Saving data in such a way that causes a thermal limit of the memory device to be exceeded may cause loss of stored data and/or device over-heating. As discussed herein, a memory controller associated with the processing circuitry may determine whether a thermal limit is expected to be exceeded for a current memory writing operation. When the thermal limit is expected to be exceeded, the memory controller may respond by modifying the memory operation in such a manner that the thermal limit is not exceeded, thereby improving operation of at least the memory device and/or memory controller.

Abstract: Methods, apparatuses, and systems for error recovery in memory devices are described. A die-level redundancy scheme may be employed in which parity data associated with particular die may be stored. An example apparatus may include a printed circuit board and memory devices. Each memory device may be each disposed on a planar surface of the printed circuit board and may each include two or more memory die. The apparatus may also include multiple channels communicatively coupled to the two or more memory die and a memory controller. The memory controller may be communicatively coupled to the multiple channels and may deterministically maintain a redundancy scheme via data transmission through the multiple channels. The memory controller may also update memory operation information appended to the enhanced codeword in response to a memory operation request.

Abstract: A method for wear leveling memory elements in a memory component of a memory subsystem is described. The method includes a memory subsystem receiving a write request that includes user data and a logical address, removing a next physical address from a next address queue, which stores physical addresses that are designated to be used for fulfilling write requests, and writing the user data to the next physical address in the memory component. Further, the memory subsystem locates, in a logical-to-physical table, an entry associated with the logical address of the write request and includes an old physical address that is mapped to the logical address of the write request. The memory subsystem adds the old physical address to a disposal address queue, wherein the disposal address queue stores physical addresses that are not designated to be used for fulfilling write requests.