Patents by Inventor Richard A. Burton
Richard A. Burton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948602Abstract: Example control circuitry, data storage devices, and methods to provide a spiral data track format that is different from the underlying servo track format are described. The data storage device may include a storage medium configured with a plurality of tracks in at least one continuous spiral pattern and a head actuated over the storage medium. The data tracks may be written to the storage medium with track lengths that are different than a single revolution of the storage medium.Type: GrantFiled: June 29, 2022Date of Patent: April 2, 2024Assignee: Western Digital Technologies, Inc.Inventors: Weldon M. Hanson, Richard Galbraith, Iouri Oboukhov, Niranjay Ravindran, Derrick Burton
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Publication number: 20240097003Abstract: A bipolar junction transistor (BJT) may include a substrate defining a collector region therein. A first superlattice may be on the substrate including a plurality of stacked groups of first layers, with each group of first layers including a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non-semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions. Furthermore, a base may be on the first superlattice, and a second superlattice may be on the base including a second plurality of stacked groups of second layers, with each group of second layers including a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions. An emitter may be on the second superlattice.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventor: Richard BURTON
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Publication number: 20240097026Abstract: A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Inventors: HIDEKI TAKEUCHI, RICHARD BURTON, YUNG-HSUAN YANG
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Patent number: 11935940Abstract: A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a base on the first superlattice, and forming a second superlattice on the base comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming an emitter on the second superlattice.Type: GrantFiled: July 26, 2022Date of Patent: March 19, 2024Assignee: ATOMERA INCORPORATEDInventor: Richard Burton
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Patent number: 11923431Abstract: A bipolar junction transistor (BJT) may include a substrate defining a collector region therein. A first superlattice may be on the substrate including a plurality of stacked groups of first layers, with each group of first layers including a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non-semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions. Furthermore, a base may be on the first superlattice, and a second superlattice may be on the base including a second plurality of stacked groups of second layers, with each group of second layers including a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions. An emitter may be on the second superlattice.Type: GrantFiled: July 26, 2022Date of Patent: March 5, 2024Assignee: ATOMERA INCORPORATEDInventor: Richard Burton
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Patent number: 11869968Abstract: A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.Type: GrantFiled: April 12, 2022Date of Patent: January 9, 2024Assignee: ATOMERA INCORPORATEDInventors: Hideki Takeuchi, Richard Burton, Yung-Hsuan Yang
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Patent number: 11734141Abstract: Aspects of the invention include receiving system data associated with a first system, the first system comprising a plurality of system components, wherein the system data comprises component data for each system component in the plurality of system components, obtaining historical performance data for each system component in the plurality of system components, determining at least one testing constraint associated with the first system, determining a test environment for the first system, the test environment comprising a plurality of test cases for the first system based on the system data, the historical performance data, and the at least one testing constraint, and executing the test environment on the first system.Type: GrantFiled: July 14, 2021Date of Patent: August 22, 2023Assignee: International Business Machines CorporationInventors: David Verburg, Gábor Andorkó, Oscar Alejandro de la Torre Del Rio, Richard Burton Finch
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Patent number: 11664427Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.Type: GrantFiled: May 23, 2022Date of Patent: May 30, 2023Assignee: ATOMERA INCORPORATEDInventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
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Publication number: 20230148175Abstract: A method for managing a virtual fence for a secondary device with respect to a controller device includes activating the controller device associated with a first object and a secondary device associated with a second object. The method includes establishing the virtual fence for the controller device and the secondary device, where the first virtual fence surrounds the secondary device and the controller device is positioned within the first virtual fence. The method includes receiving, from the controller device, a ping with location information for the controller device and the secondary device. The method includes, responsive to determining an adjustment to the first virtual fence is required, adjusting the first virtual fence based on a movement of the secondary device from a first location to a second location.Type: ApplicationFiled: November 8, 2021Publication date: May 11, 2023Inventors: Lowell Thomason, Jessica Wandrey, Mark E. Maresh, Richard Burton Finch, Bradley Smoley
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Patent number: 11567824Abstract: Restricting use of a selected input in recovery from system failures. A testing system obtains, based on failure of a system, an indication of one or more tasks to be performed. The testing system automatically determines whether a user is to perform one or more actions to alter execution of the one or more tasks. The automatically determining is based on an indication of whether a knowledge transfer score of the user meets at least one predefined criterion. Based on knowledge transfer score meeting the at least one predefined criterion, the one or more actions are performed.Type: GrantFiled: December 15, 2020Date of Patent: January 31, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chanchal Saha, Kanayo George Okonji, Richard Burton Finch, Jeffrey Willoughby, Marc Henri Coq
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Publication number: 20230015477Abstract: Aspects of the invention include receiving system data associated with a first system, the first system comprising a plurality of system components, wherein the system data comprises component data for each system component in the plurality of system components, obtaining historical performance data for each system component in the plurality of system components, determining at least one testing constraint associated with the first system, determining a test environment for the first system, the test environment comprising a plurality of test cases for the first system based on the system data, the historical performance data, and the at least one testing constraint, and executing the test environment on the first system.Type: ApplicationFiled: July 14, 2021Publication date: January 19, 2023Inventors: David Verburg, Gábor Andorkó, Oscar Alejandro de la Torre Del Rio, Richard Burton Finch
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Publication number: 20220367676Abstract: A bipolar junction transistor (BJT) may include a substrate defining a collector region therein. A first superlattice may be on the substrate including a plurality of stacked groups of first layers, with each group of first layers including a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non-semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions. Furthermore, a base may be on the first superlattice, and a second superlattice may be on the base including a second plurality of stacked groups of second layers, with each group of second layers including a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions. An emitter may be on the second superlattice.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventor: RICHARD BURTON
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Publication number: 20220367675Abstract: A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a base on the first superlattice, and forming a second superlattice on the base comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming an emitter on the second superlattice.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventor: RICHARD BURTON
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Patent number: 11489344Abstract: In an approach for selecting a battery charging rate, a processor, responsive to an electronic device with a rechargeable battery being connected to a battery charging device, identifies a current battery status of the rechargeable battery. A processor determines a disconnect time of the battery charging device. A processor determines a charge level required. A processor determines a charging profile based on the current battery status, the disconnect time of battery charging device, and the charge level required. A processor sends the charging profile to the battery charging device.Type: GrantFiled: March 10, 2020Date of Patent: November 1, 2022Assignee: International Business Machines CorporationInventors: John S. Werner, Enver Candan, Brianna Malcolm, Matthew Alzamora, Hanami Robles Chacon, Richard Burton Finch
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Publication number: 20220285498Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: ROBERT JOHN STEPHENSON, RICHARD BURTON, DMITRI CHOUTOV, NYLES WYNN CODY, DANIEL CONNELLY, ROBERT J. MEARS, ERWIN TRAUTMANN
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Patent number: 11437486Abstract: A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a base on the first superlattice, and forming a second superlattice on the base comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming an emitter on the second superlattice.Type: GrantFiled: June 26, 2020Date of Patent: September 6, 2022Assignee: ATOMERA INCORPORATEDInventor: Richard Burton
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Patent number: 11437487Abstract: A bipolar junction transistor (BJT) may include a substrate defining a collector region therein. A first superlattice may be on the substrate including a plurality of stacked groups of first layers, with each group of first layers including a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non-semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions. Furthermore, a base may be on the first superlattice, and a second superlattice may be on the base including a second plurality of stacked groups of second layers, with each group of second layers including a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions. An emitter may be on the second superlattice.Type: GrantFiled: June 26, 2020Date of Patent: September 6, 2022Assignee: ATOMERA INCORPORATEDInventor: Richard Burton
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Publication number: 20220238710Abstract: A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.Type: ApplicationFiled: April 12, 2022Publication date: July 28, 2022Inventors: HIDEKI TAKEUCHI, RICHARD BURTON, YUNG-HSUAN YANG
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Patent number: 11387325Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.Type: GrantFiled: November 23, 2020Date of Patent: July 12, 2022Assignee: ATOMERA INCORPORATEDInventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
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Publication number: 20220188181Abstract: Restricting use of a selected input in recovery from system failures. A testing system obtains, based on failure of a system, an indication of one or more tasks to be performed. The testing system automatically determines whether a user is to perform one or more actions to alter execution of the one or more tasks. The automatically determining is based on an indication of whether a knowledge transfer score of the user meets at least one predefined criterion. Based on knowledge transfer score meeting the at least one predefined criterion, the one or more actions are performed.Type: ApplicationFiled: December 15, 2020Publication date: June 16, 2022Inventors: Chanchal Saha, Kanayo George Okonji, Richard Burton Finch, Jeffrey Willoughby, Marc Henri Coq