Patents by Inventor Richard A. Burton

Richard A. Burton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10879356
    Abstract: A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and forming a conductive body within the trench.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 29, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
  • Patent number: 10879357
    Abstract: A method for making semiconductor device may include forming a hyper-abrupt junction region on a substrate and including a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The first, second, and the superlattice layers may be U-shaped. The method may further include forming a gate dielectric layer on the second semiconductor layer of the hyper-abrupt junction region, forming a gate electrode on the gate dielectric layer, and forming spaced apart source and drain regions adjacent the hyper-abrupt junction region.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: December 29, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Richard Burton, Marek Hytha, Robert J. Mears
  • Patent number: 10868120
    Abstract: A method for making a semiconductor device may include forming a hyper-abrupt junction region on a substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a first contact coupled to the hyper-abrupt junction regions, and forming a second contact coupled to the substrate to define a varactor.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: December 15, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Richard Burton, Marek Hytha, Robert J. Mears
  • Patent number: 10854717
    Abstract: A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice, with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 1, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10847618
    Abstract: A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device may further include a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 24, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10840336
    Abstract: A semiconductor device may include a semiconductor layer and at least one contact in the semiconductor layer. The contact may include at least one oxygen monolayer constrained within a crystal lattice of adjacent semiconductor portions of the semiconductor layer and spaced apart from a surface of the semiconductor layer by between one and four monolayers, and a metal layer on the surface of the semiconductor layer above the at least one oxygen monolayer. The semiconductor portion between the oxygen monolayer and the metal layer may have a dopant concentration of 1×1021 atoms/cm3 or greater.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 17, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Daniel Connelly, Marek Hytha, Hideki Takeuchi, Richard Burton, Robert J. Mears
  • Patent number: 10840337
    Abstract: A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 17, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10840388
    Abstract: A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first contact coupled to the hyper-abrupt junction region, and a second contact coupled to the substrate to define a varactor.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: November 17, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Richard Burton, Marek Hytha, Robert J. Mears
  • Patent number: 10840335
    Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region. The method may further include forming a body contact in the semiconductor layer and including a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 17, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10825901
    Abstract: A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The first, second, and the superlattice layers may be U-shaped. The semiconductor device may further include a gate dielectric layer on the second semiconductor layer of the hyper-abrupt junction region, a gate electrode on the gate dielectric layer, and spaced apart source and drain regions adjacent the hyper-abrupt junction region.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: November 3, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Richard Burton, Marek Hytha, Robert J. Mears
  • Patent number: 10825902
    Abstract: A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may further include a first contact coupled to the hyper-abrupt junction regions and a second contact coupled to the substrate to define a varactor. The first and second superlattices may each include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: November 3, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Richard Burton, Marek Hytha, Robert J. Mears
  • Publication number: 20200343380
    Abstract: A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.
    Type: Application
    Filed: April 21, 2020
    Publication date: October 29, 2020
    Inventors: HIDEKI TAKEUCHI, Richard Burton, Yung-Hsuan Yang
  • Publication number: 20200343367
    Abstract: A method for making a semiconductor device may include forming spaced apart first and second doped regions in a substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The method may further include forming a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a gate overlying the asymmetric channel.
    Type: Application
    Filed: April 21, 2020
    Publication date: October 29, 2020
    Inventors: HIDEKI TAKEUCHI, Richard Burton, Yung-Hsuan Yang
  • Patent number: 10818755
    Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 27, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Publication number: 20200313978
    Abstract: Provided are systems, methods, and computer products for interactive cable routing and planning optimization for customized hardware configurations. An example method includes receiving a set of cable characteristics and a set of user selections, in which the set of user selections are received via a graphical user interface (GUI). Identifying possible cabling routes for a hardware configuration based, at least in part, on available plug start and termination locations. Ranking each of the possible cabling routes based, at least in part, on a prioritized list of optimization criteria and the set of cable characteristics. Generating a suggested cabling configuration for one or more applications based, at least in part, on the set of cable characteristics, the set of user selections, and the ranking. Outputting the suggested cabling configuration to the user by at least providing a three-dimensional view of the suggested cabling configuration via the GUI.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Adam Benjamin Childers, Ryan Elsasser, Karl Owen Casserly, Richard Burton Finch, Paul Samaniego, Michael J. Doscher, Mateusz Koziol
  • Patent number: 10777451
    Abstract: A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and a conductive body within the trench.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 15, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J Mears, Erwin Trautmann
  • Publication number: 20200227037
    Abstract: Methods, systems and computer program products for operating a voice response system are provided. Aspects include receiving, by the voice response system, a voice command from a first user and determining an operating mode of the voice response system. Aspects also include obtaining, by the voice response system, a response preference of the first user and determining a response to the voice command. The response is determined based at least in part on the response preference of the first user and the operating mode of the voice response system. Aspects also include providing the response to the first user.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Inventors: ERIC V. KLINE, RICHARD BURTON FINCH, SARBAJIT K. RAKSHIT
  • Publication number: 20200161428
    Abstract: A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice, with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: HIDEKI TAKEUCHI, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Publication number: 20200161426
    Abstract: A semiconductor device may include a semiconductor layer and at least one contact in the semiconductor layer. The contact may include at least one oxygen monolayer constrained within a crystal lattice of adjacent semiconductor portions of the semiconductor layer and spaced apart from a surface of the semiconductor layer by between one and four monolayers, and a metal layer on the surface of the semiconductor layer above the at least one oxygen monolayer. The semiconductor portion between the oxygen monolayer and the metal layer may have a dopant concentration of 1×1021 atoms/cm3 or greater.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: DANIEL CONNELLY, Marek Hytha, Hideki Takeuchi, Richard Burton, Robert J. Mears
  • Publication number: 20200161429
    Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: HIDEKI TAKEUCHI, DANIEL CONNELLY, MAREK HYTHA, RICHARD BURTON, ROBERT J. MEARS