Abstract: A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device may further include a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region. The method may further include forming a body contact in the semiconductor layer and including a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.

Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.

Abstract: A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The at least one dopant diffusion blocking superlattice comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.

Abstract: A FINFET may include a semiconductor fin, spaced apart source and drain regions in the semiconductor fin with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.

Abstract: A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and forming a conductive body within the trench.

Abstract: A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and a conductive body within the trench.

Abstract: A wireless broadcasting device, systems including the device, and methods of programming and using the device are disclosed. The wireless broadcasting device is powered using power over Ethernet and can be used to provide proximity-based capabilities to devices that otherwise do not have such functions.

Abstract: A wireless broadcasting device, systems including the device, and methods of programming and using the device are disclosed. The wireless broadcasting device is powered using power over Ethernet and can be used to provide proximity-based capabilities to devices that otherwise do not have such functions.

Abstract: A package structure and method for forming the same are provided. The package structure includes a first die, and the first die includes a first magnetic pad formed over a first substrate. The package structure includes a second die, and the second die includes a second magnetic pad formed over a second substrate. The package structure also includes a hybrid bonding structure formed between the first die and the second die of the second wafer. The hybrid bonding structure includes a magnetic bonding structure which is made of the first magnetic pad and the second magnetic layer.

Abstract: A package structure and method for forming the same are provided. The package structure includes a first die, and the first die includes a first magnetic pad formed over a first substrate. The package structure includes a second die, and the second die includes a second magnetic pad formed over a second substrate. The package structure also includes a hybrid bonding structure formed between the first die and the second die of the second wafer. The hybrid bonding structure includes a magnetic bonding structure which is made of the first magnetic pad and the second magnetic layer.

Abstract: A wireless broadcasting device, systems including the device, and methods of programming and using the device are disclosed. The wireless broadcasting device is powered using power over Ethernet and can be used to provide proximity-based capabilities to devices that otherwise do not have such functions.

Abstract: An electric current flow indicator senses electrical current flowing through an electrical device and produces a visible feedback to indicate proper operation. The current flow indicator has a voltage and current regulation circuit having first and second inputs connected to first and second conductors, respectively. The circuit converts an AC line voltage carried by an electrical supply cord into a limited low voltage DC current. A toroidal core inductor coil and at least one current indicating LED are connected to the circuit. The first conductor passes through a center of the inductor coil. A transistor amplifier is connected to an output of the inductor coil for energizing the current indicating LED when an electrical current conducts through the first conductor. The flow indicator can be integrated into an electrical supply cord, a male or female electrical cord end, a single or duplex electrical outlet, or a universal plugin adapter.

Abstract: An electric current flow indicator senses electrical current flowing through an electrical device and produces a visible feedback to indicate proper operation. The current flow indicator has a voltage and current regulation circuit having first and second inputs connected to first and second conductors, respectively. The circuit converts an AC line voltage carried by an electrical supply cord into a limited low voltage DC current. A toroidal core inductor coil and at least one current indicating LED are connected to the circuit. The first conductor passes through a center of the inductor coil. A transistor amplifier is connected to an output of the inductor coil for energizing the current indicating LED when an electrical current conducts through the first conductor. The flow indicator can be integrated into an electrical supply cord, a male or female electrical cord end, a single or duplex electrical outlet, or a universal plugin adapter.

Abstract: An ultrasonic pulse echo apparatus detects an object that is moving with respect to stationary objects. An ultrasonic transducer transmits a series of ultrasound pulses in a direction that intersects a path of the moving object. An ultrasound receiver receives a series of lines of echoes from objects in the field of view of the ultrasonic signal. Each echo line corresponds to one of the ultrasonic pulses. A signal processor processes the echo lines from the moving object. The echo lines are time shifted by different amounts and combined at different time shifts to produce different composite lines. The composite line having an optimal signal-to-noise ratio is selected. Other signal processing enhancements are performed.

Abstract: An ultrasonic pulse echo apparatus detects an object that is moving with respect to stationary objects. An ultrasonic transducer transmits a series of ultrasound pulses in a direction that intersects a path of the moving object. An ultrasound receiver receives a series of lines of echoes from objects in the field of view of the ultrasonic signal. Each echo line corresponds to one of the ultrasonic pulses. A signal processor processes the echo lines from the moving object. The echo lines are time shifted by different amounts and combined at different time shifts to produce different composite lines. The composite line having an optimal signal-to-noise ratio is selected. Other signal processing enhancements are performed.

Abstract: An alkaline cell having a flat housing, preferably of cuboid shape. The cell can have an anode comprising zinc and a cathode comprising MnO2. The housing can have a relatively small overall thickness, typically between about 5 and 10 mm. Cell contents can be supplied through an open end in the housing and an end cap assembly inserted therein to seal the cell. There can be a gap between separator and cathode for insertion of additional electrolyte. The end cap assembly includes a vent mechanism, preferably a grooved vent, which can activate, when gas pressure within the cell reaches a threshold level typically between about 250 and 800 psig (1724×103 and 5515×103 pascal gage). The cell can have a supplemental vent mechanism such as a laser welded region on the surface of the housing which may activate at higher pressure levels.

Abstract: An alkaline cell having a flat housing, preferably of cuboid shape. The cell can have an anode comprising zinc and a cathode comprising MnO2. The housing can have a relatively small overall thickness, typically between about 5 and 10 mm. Cell contents can be supplied through an open end in the housing and an end cap assembly inserted therein to seal the cell. There can be a gap between separator and cathode for insertion of additional electrolyte. The end cap assembly includes a vent mechanism, preferably a grooved vent, which can activate, when gas pressure within the cell reaches a threshold level typically between about 250 and 800 psig (1724×103 and 5515×103 pascal gage). The cell can have a supplemental vent mechanism such as a laser welded region on the surface of the housing which may activate at higher pressure levels.