Abstract: A device manufacturing method includes a transfer of a pattern from a patterning device onto a substrate. The device manufacturing method further includes transferring a pattern of a main mark to a base layer for forming an alignment mark; depositing a pattern receiving layer on the base layer; in a first lithographic process, aligning, by using the main mark, a first mask that includes a first pattern and a local mark pattern, and transferring the first pattern and the local mark pattern to the pattern receiving layer; aligning, by using the local mark pattern, a second mask including a second pattern relative to the pattern receiving layer; and in a second lithographic process, transferring the second pattern to the pattern receiving layer; the first and second patterns being configured to form an assembled pattern.

Abstract: In an embodiment, a method of creating an alignment mark on a substrate includes forming a plurality of lines segmented into electrically conducting line segments and space segments, thereby forming spaces between the lines to form a macroscopic structure in a first layer of the substrate, creating a plurality of electrically conducting trenches in a second layer of the substrate, and arranging the plurality of trenches to be in electrical contact with the line segments and overlapping the space segments at least partially.

Abstract: An electrical connector sub-assembly including a housing having at least one electrical contact receiving area configured to receive an electrical contact; and a terminal position assurance (TPA) member located on a front section of the housing. The TPA member is laterally movable on the front section between an unlocked position and a locked position. The TPA member comprises two spaced sections configured to lock the electrical contact in the electrical contact receiving area at two spaced locations when the TPA member is moved to the locked position. This prevents unintentional withdrawal of the electrical contact from the electrical contact receiving area.

Abstract: An alignment system for a lithographic apparatus has a source of alignment radiation; a detection system that has a first detector channel and a second detector channel; and a position determining unit in communication with the detection system. The position determining unit is constructed to process information from said first and second detector channels in a combination to determine a position of an alignment mark on a work piece, the combination taking into account a manufacturing process of the work piece. A lithographic apparatus has the above mentioned alignment system. Methods of alignment and manufacturing devices with a lithographic apparatus use the above alignment system and lithographic apparatus, respectively.

Abstract: Alignment marks for use on substrates. In one example, the alignment marks consist of periodic 2-dimensional arrays of structures, the spacing of the structures being smaller than an alignment beam but larger than an exposure beam.

Abstract: End of line effect can occur during manufacture of components using a lithographic apparatus. These end of line effects can result in line end shortening of the features being manufactured. Such line end shortening may have an adverse impact on the component being manufactured. It is therefore desirable to predict and/or monitor the line end shortening. A test pattern is provided that has two separate areas such that, as designed, when the two areas are illuminated with radiation (for example from an angle-resolved scatterometer) they result in diffused radiation with asymmetry that is equal in sign to each other, but opposite in magnitude. When the test pattern is actually manufactured, line end shortening occurs, and so the asymmetry of the two areas are not equal and opposite. From the measured asymmetry of the manufactured test pattern, the amount of line end shortening that has occurred can be estimated.

Abstract: An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.

Abstract: A semiconductor wafer is aligned using a double patterning process. A first resist layer having a first optical characteristic is deposited and foams at least one alignment mark. The first resist layer is developed. A second resist layer having a second optical characteristic is deposited over the first resist layer. The combination of first and second resist layers and alignment mark has a characteristic such that radiation of a pre-determined wavelength incident on the alignment mark produces a first or higher order diffraction as a function of the first and second optical characteristics.

Abstract: An electrical connector sub-assembly including a housing having at least one electrical contact receiving area configured to receive an electrical contact; and a terminal position assurance (TPA) member located on a front section of the housing. The TPA member is laterally movable on the front section between an unlocked position and a locked position. The TPA member comprises two spaced sections configured to lock the electrical contact in the electrical contact receiving area at two spaced locations when the TPA member is moved to the locked position. This prevents unintentional withdrawal of the electrical contact from the electrical contact receiving area.

Abstract: A device manufacturing method includes a transfer of a pattern from a patterning device onto a substrate. The device manufacturing method further includes transferring a pattern of a main mark to a base layer for forming an alignment mark; depositing a pattern receiving layer on the base layer; in a first lithographic process, aligning, by using the main mark, a first mask that includes a first pattern and a local mark pattern, and transferring the first pattern and the local mark pattern to the pattern receiving layer; aligning, by using the local mark pattern, a second mask including a second pattern relative to the pattern receiving layer; and in a second lithographic process, transferring the second pattern to the pattern receiving layer; the first and second patterns being configured to form an assembled pattern.

Abstract: A method of forming features, e.g. contact holes, at a higher density than is possible with conventional lithographic techniques involves forming an array of sacrificial positive features, conformally depositing a sacrificial layer so that negative features are formed interleaved with the positive features, directionally etching the sacrificial layer and removing the sacrificial features. The result is an array of holes at a higher density than the original sacrificial features. These may then be transferred into the underlying substrate using a desired process. Also, the method may be repeated to create arrays at even higher densities.

Abstract: A mark used in the determination of overlay error comprises sub-features, the sub-features having a smallest pitch approximately equal to the smallest pitch of the product features. The sensitivity to distortions and aberrations is similar as that for the product features. When the mark is developed the sub-features merge and the outline of the larger feature is developed.

Abstract: An alignment system for a lithographic apparatus has a source of alignment radiation; a detection system that has a first detector channel and a second detector channel; and a position determining unit in communication with the detection system. The position determining unit is constructed to process information from said first and second detector channels in a combination to determine a position of an alignment mark on a work piece, the combination taking into account a manufacturing process of the work piece. A lithographic apparatus has the above mentioned alignment system. Methods of alignment and manufacturing devices with a lithographic apparatus use the above alignment system and lithographic apparatus, respectively.

Abstract: The invention includes a lithographic system having a first source for generating radiation with a first wavelength and an alignment system with a second source for generating radiation with a second wavelength. The second wavelength is larger than the first wavelength. A marker structure is provided having a first layer and a second layer. The second layer is present either directly or indirectly on top of said first layer. The first layer has a first periodic structure and the second layer has a second periodic structure. At least one of the periodic structures has a plurality of features in at least one direction with a dimension smaller than 400 nm. Additionally, a combination of the first and second periodic structure forms a diffractive structure arranged to be illuminated by radiation with the second wavelength.

Abstract: Coated fertilizer wherein the fertilizer and animal feed comprises particles coated with a biomass composition comprising 5-35 wt. % solid biomass particles with a D50 between 0 and 250 ?m and a D90 of less than 400 ?m and 95-65 wt. % oil, a biomass composition wherein the biomass composition comprises solid biomass particles with a D50 between 0 and 250 ?m and a D30 of less than 400 ?m and a process for the production of a biomass composition wherein a biomass composition comprising solid particles having a D50 between 100 and 1000 ?m is filtrated and the residue is grinded until the solid particles have a D50 between =0 and 250 ?m and a D90 of less than 400 ?m.

Abstract: A method for providing temporary measurement targets during a multiple patterning process which can be removed in the completion of the process. The metrology target is defined in either the first or the second exposure of a multiple exposure process and whether or not it is temporary or made permanent is selected according to whether or not the area of the target is covered or cleared out in the other exposure. The use of temporary targets reduces the amount of space on the substrate that must be devoted to targets.

Abstract: The present invention relates to alignment marks for use on substrates, the alignment marks consisting of periodic 2-dimensional arrays of structures, the spacing of the structures being smaller than an alignment beam but larger than an exposure beam and the width of the structures varying sinusoidally from one end of an array to the other.

Abstract: A method is described for alignment of a substrate during a double patterning process. A first resist layer containing at least one alignment mark is formed on the substrate. After the first resist layer is developed, a second resist layer is deposited over the first resist layer, leaving a planar top surface (i.e., without topography). By baking the second resist layer appropriately, a symmetric alignment mark is formed in the second resist layer with little or no offset error from the alignment mark in the first resist layer. The symmetry of the alignment mark formed in the second resist can be enhanced by appropriate adjustments of the respective thicknesses of the first and second resist layers, the coating process parameters, and the baking process parameters.

Abstract: A system and method of manufacturing a semiconductor device lithographically and an article of manufacture involving a lithographic double patterning process having a dye added to either the first or second lithographic pattern are provided. The dye is used to detect the location of the first lithographic pattern and to directly align the second lithographic pattern to it. The day may be fluorescent, luminescent, absorbent, or reflective at a specified wavelength or a given wavelength band. The wavelength may correspond to the wavelength of an alignment beam. The dye allows for detection of the first lithographic pattern even when it is over coated with a radiation sensitive-layer (e.g., resist).

Abstract: An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.