Abstract: Disclosed herein are various methods of forming replacement gate structures on semiconductor devices and devices incorporating such gate structures. In one example, the device includes a plurality of gate structures and at least one sidewall spacer positioned proximate each of the gate structures, a metal silicide region in a source/drain region formed in a substrate, wherein the metal silicide region extend laterally so as to contact the sidewall spacer positioned proximate each of the gate structures and a conductive contact positioned between the gate structures that conductively contacts the metal silicide region, wherein the conductive contact has a bottom portion that is wider than an upper portion of the conductive contact.

Abstract: Embodiments of the present invention are directed systems and methods for reading the resistance states of crossbar junctions of a crossbar array. In one aspect, a system includes one or more sense amplifiers (512-514) connected to column wires of the crossbar array, a reference row wire (516) connected to each sense amp, and a wire driver (518) connected to the reference row wire and configured to drive the reference row wire. The sense amplifiers are configured so that when a selected row wire of the crossbar array is driven by a sense voltage, the column wires are held at approximately zero volts and pass currents through the column wires and sense amplifiers to the reference row wire so that resistive voltage losses along the reference row wire substantially mirror the resistive voltage losses along the selected row wire, allowing the sense amplifiers to determine the crossbar junction resistance states.

Abstract: The work function of a high-k gate electrode structure may be adjusted in a late manufacturing stage on the basis of a lanthanum species in an N-channel transistor, thereby obtaining the desired high work function in combination with a typical conductive barrier material, such as titanium nitride. For this purpose, in some illustrative embodiments, the lanthanum species may be formed directly on the previously provided metal-containing electrode material, while an efficient barrier material may be provided in the P-channel transistor, thereby avoiding undue interaction of the lanthanum species in the P-channel transistor.

Abstract: When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures.

Abstract: When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.

Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.

Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.

Abstract: Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures.

Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.

Abstract: In a manufacturing strategy for providing high-k metal gate electrode structures in an early manufacturing stage, process-related non-uniformities during and after the patterning of the gate electrode structures may be reduced by providing a superior surface topography. To this end, the material loss in the isolation region may generally be reduced and a more symmetrical exposure to reactive etch atmospheres during the subsequent removal of the growth mask may be accomplished by providing an additional etch mask when removing the growth mask from the active regions of N-channel transistors, after the growth of the threshold adjusting semiconductor material on the active regions of the P-channel transistors.

Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.

Abstract: In sophisticated approaches for forming high-k metal gate electrode structures in an early manufacturing stage, a threshold adjusting semiconductor alloy may be deposited on the basis of a selective epitaxial growth process without affecting the back side of the substrates. Consequently, any negative effects, such as contamination of substrates and process tools, reduced surface quality of the back side and the like, may be suppressed or reduced by providing a mask material and preserving the material at least during the selective epitaxial growth process.

Abstract: Gate failures in sophisticated high-k metal gate electrode structures formed in an early manufacturing stage may be reduced by forming a protective liner material after the incorporation of a strain-inducing semiconductor alloy and prior to performing any critical wet chemical processes. In this manner, attacks in the sensitive gate materials after the incorporation of the strain-inducing semiconductor material may be avoided, without influencing the further processing of the device. In this manner, very sophisticated circuit designs may be applied in sophisticated gate first approaches.

Abstract: In a manufacturing strategy for providing high-k metal gate electrode structures in an early manufacturing stage, process-related non-uniformities during and after the patterning of the gate electrode structures may be reduced by providing a superior surface topography. To this end, the material loss in the isolation region may generally be reduced and a more symmetrical exposure to reactive etch atmospheres during the subsequent removal of the growth mask may be accomplished by providing an additional etch mask when removing the growth mask from the active regions of N-channel transistors, after the growth of the threshold adjusting semiconductor material on the active regions of the P-channel transistors.

Abstract: In sophisticated approaches for forming high-k metal gate electrode structures in an early manufacturing stage, a threshold adjusting semiconductor alloy may be deposited on the basis of a selective epitaxial growth process without affecting the back side of the substrates. Consequently, any negative effects, such as contamination of substrates and process tools, reduced surface quality of the back side and the like, may be suppressed or reduced by providing a mask material and preserving the material at least during the selective epitaxial growth process.

Abstract: In sophisticated approaches for forming high-k metal gate electrode structures in an early manufacturing stage, a threshold adjusting semiconductor alloy may be deposited on the basis of a selective epitaxial growth process without affecting the back side of the substrates. Consequently, any negative effects, such as contamination of substrates and process tools, reduced surface quality of the back side and the like, may be suppressed or reduced by providing a mask material and preserving the material at least during the selective epitaxial growth process.

Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.

Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.

Abstract: Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.

Abstract: According to one exemplary embodiment, a switching module includes a first harmonic phase tuning filter coupled to a first input of an RF switch. The first harmonic phase tuning filter is configured to provide an output impedance that substantially matches an input impedance of the RF switch at approximately a fundamental frequency and to provide a high impedance at approximately a harmonic frequency generated by the RF switch. The first harmonic phase tuning filter includes an LC circuit coupled between input and output terminals of the first harmonic phase tuning filter and tuned to provide the high impedance at approximately the harmonic frequency generated by the RF switch. The RF switching module further includes a second harmonic phase tuning filter coupled to a second input of the RF switch. The first and second harmonic phase tuning filters can be fabricated on a single semiconductor die.