Abstract: The present invention provides an enhanced DC-NC (eDC-NC) system and method that enables ultra-reliable networking, provides near-instant latency, reduces power consumption while recovering from simultaneous multiple link/node failures and improves the throughput for a wide variety of network architectures.

Abstract: A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

Abstract: A DAC driver includes a number of DAC drivers coupled to a load network. A first DAC driver includes a first set of data switches that can be controlled by a first digital input signal. The first DAC driver further includes a first set of output switches, a first set of dump switches and a first set of current sources. Another DAC driver includes a second set of output switches, dump switches, and current sources. The first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the first set of current sources to the load network. The first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or the second set current sources into a respective dump load.

Abstract: A band-pass clock distribution circuit includes a clock tree circuit including at least one clock buffer circuit. The clock tree circuit may be configured to receive a first clock signal from a clock generator circuit and to generate a second clock signal based on the first clock signal. A band-pass filter may be configured to receive the second clock signal and to provide a third clock signal to one or more load circuits. The band-pass filter includes a filtering resonant network including a first inductor and a second inductor coupled to one another at a center tap. The filtering resonant network is configurable to resonate with a parasitic capacitance associated with the one or more load circuits. A portion of the band-pass filter is integrated with the clock tree circuit.

Abstract: A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

Abstract: A DAC driver includes a number of DAC drivers coupled to a load network. A first DAC driver includes a first set of data switches that can be controlled by a first digital input signal. The first DAC driver further includes a first set of output switches, a first set of dump switches and a first set of current sources. Another DAC driver includes a second set of output switches, dump switches, and current sources. The first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the first set of current sources to the load network. The first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or the second set current sources into a respective dump load.

Abstract: A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.

Abstract: A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

Abstract: System and method for providing patient-specific models to distinguish between epochs of electrocardiograms (ECGs) located far away from atrial fibrillation rhythms and those located just prior to the onset of those episodes, to provide for the prediction of the onset of an occurrence of atrial fibrillation (AF) in the patient.

Abstract: A double-balanced radio-frequency (RF) mixing digital-to-analog converter (DAC) apparatus includes a load network, a first set of resistive DAC driver circuits and a first mixing core. The first mixing core can receive first RF input signals from the first set of resistive DAC driver circuits and can provide a first mixed signal to the load network. The first mixing core includes a first input differential pair coupled to two first cross-coupled differential pairs. The first input differential pair can receive first RF input signals at respective first input nodes. Each of the two first cross-coupled differential pairs can receive first positive and negative local oscillator (LO) signals at corresponding first input nodes. The first mixing core can mix the first RF input signals with the first positive and negative LO signals.

Abstract: A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.

Abstract: An AC capable power amplifier arrangement is realized that includes a buck converter with a power inductor, two buck switches, and alternately a buck-boost converter using four switches, each driving an output polarity steering set of four switches. The polarity steering switches convey the converter output current to output terminals that connect to a load with a capacitor connected in parallel. A differential receiver is connected to the output terminals to provide negative feedback. A mixer receives an input voltage signal, an output of the differential receiver, and output from a triangle wave generator. A set of two comparators for buck amplifier conversion, or four comparators for buck-boost amplifier conversion, each receives an output of the mixer. Each of the comparators produces a respective output for driving the converter switches through simple steering logic interfaces between the comparators, the converter components and a polarity steering output stage.

Abstract: A DAC driver includes a number of DAC drivers coupled to a load network. A first DAC driver includes a first set of data switches that can be controlled by a first digital input signal. The first DAC driver further includes a first set of output switches, a first set of dump switches and a first set of current sources. Another DAC driver includes a second set of output switches, dump switches, and current sources. The first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the first set of current sources to the load network. The first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or the second set current sources into a respective dump load.

Abstract: The present invention provides an enhanced DC-NC (eDC-NC) system and method that enables ultra-reliable networking, provides near-instant latency, reduces power consumption while recovering from simultaneous multiple link/node failures and improves the throughput for a wide variety of network architectures.

Abstract: A system and method for Machine-to-Machine (M2M) communication over a transmission medium, including a novel random access protocol that is easy to implement, energy efficient, scalable and compatible with the limited-power and low complexity requirements of IoT devices. The proposed protocol utilizes a form of multiple hypothesis testing at the IoT gateway to determine the number of active IoT devices operating in the transmission medium to optimize the power levels of a Successive Interference Cancellation (SIC) receiver in order to distinguish between signals transmitted from different IoT devices on the same time and frequency. The use of beamforming exploits the power and spatial domains without excessively increasing the SIC power levels and address channel access delay problems by reducing the probability of collision and consequently lowering the average back-off delay.

Abstract: Methods, apparatus, and computer-readable media are described herein related to a user interface (UI) for a computing device, such as head-mountable device (HMD). The UI allows a user of the HMD to navigate through a timeline of ordered screens or cards shown on the graphic display of the HMD. The cards on the timeline may be chronologically ordered based on times associated with each card. Numerous cards may be added to the timeline such that a user may scroll through the timeline to search for a specific card. The HMD may be configured to group cards on the timeline. The cards may be grouped by multiple time periods and by various content types within each respective time period. The cards may also be grouped based on durations between the present/on-going time period and each respective time period.

Abstract: An AC capable power amplifier arrangement is realized that includes a buck converter with a power inductor, two buck switches, and alternately a buck-boost converter using four switches, each driving an output polarity steering set of four switches. The polarity steering switches convey the converter output current to output terminals that connect to a load with a capacitor connected in parallel. A differential receiver is connected to the output terminals to provide negative feedback. A mixer receives an input voltage signal, an output of the differential receiver, and output from a triangle wave generator. A set of two comparators for buck amplifier conversion, or four comparators for buck-boost amplifier conversion, each receives an output of the mixer. Each of the comparators produces a respective output for driving the converter switches through simple steering logic interfaces between the comparators, the converter components and a polarity steering output stage.

Abstract: Methods, apparatus, and computer-readable media are described herein related to a user interface (UI) for a computing device, such as head-mountable device (HMD). The UI allows a user of the HMD to navigate through a timeline of ordered screens or cards shown on the graphic display of the HMD. The cards on the timeline may be chronologically ordered based on times associated with each card. Numerous cards may be added to the timeline such that a user may scroll through the timeline to search for a specific card. The HMD may be configured to group cards on the timeline. The cards may be grouped by multiple time periods and by various content types within each respective time period. The cards may also be grouped based on durations between the present/on-going time period and each respective time period.

Abstract: A band-pass clock distribution circuit includes a clock tree circuit including at least one clock buffer circuit. The clock tree circuit may be configured to receive a first clock signal from a clock generator circuit and to generate a second clock signal based on the first clock signal. A band-pass filter may be configured to receive the second clock signal and to provide a third clock signal to one or more load circuits. The band-pass filter includes a filtering resonant network including a first inductor and a second inductor coupled to one another at a center tap. The filtering resonant network is configurable to resonate with a parasitic capacitance associated with the one or more load circuits. A portion of the band-pass filter is integrated with the clock tree circuit.

Abstract: A system, for example, an online system or a database system schedules requests received for execution. The system maintains consumer groups and receives a measure of amount of resources allocated for each consumer group. The system maintains a measure of accumulated elapsed time of execution of requests received from each consumer group. If the system determines that resources are available for executing a request, the system selects a request for execution from a consumer group based on the measure of accumulated elapsed time for processing queries for the consumer group and the measure of amount of resources allocated for the consumer group. The system maintains relative cumulative elapsed times of queries across consumer groups in the same ratio as the allocated share for the consumer groups. Accordingly, the system schedules requests such that each consumer group approaches its allocation of resources compared to other groups smoothly over time.