Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: In some embodiments, an optical scope includes a direct-view optics assembly including an objective lens and a viewing lens. The direct-view optics assembly may be configured to direct and focus light from a view area received by the objective lens toward the viewing lens. The optical scope may further include a selectable element accessible by a user to select one of a direct-view mode and a digital-view mode and a switchable circuit element configured to selectively interrupt a light path between the objective lens and the viewing lens in response to selection of the digital-view mode.

Abstract: In some embodiments, a firearm system can include an optical scope. The optical scope may include a direct-view optics assembly and a switchable microdisplay element. The direct-view optics assembly can include an objective lens and a viewing lens, and may be configured to direct and focus light received by the objective lens toward the viewing lens. The switchable microdisplay element may be configured to selectively interrupt a light path between the objective lens and the viewing lens to present image data to the viewing lens.

Abstract: In some embodiments, an apparatus can include an optical device configured to provide a day view image mode and a night view image mode. The optical device may include an optics assembly configured to receive light from a view area and a control circuit including one or more sensors and a display interface. The control circuit may be configured to receive a mode selection input and to selectively enable at least one of the display interface and the one or more sensors in response to the mode selection input indicating a night view image mode. The optical device may also include an optical element responsive to a signal from the control circuit to direct at least a portion of the light toward the one or more sensors.

Abstract: Provided herein are systems and methods for storing digital information by assembling an identifier nucleic acid molecule from at least a first component nucleic acid molecule and a second component nucleic acid molecule. The system may include a first printhead configured to dispense a first droplet of a first solution comprising the first component nucleic acid molecule onto a coordinate on a substrate, and a second printhead configured to dispense a second droplet of a second solution comprising the second component nucleic acid molecule onto the coordinate on the substrate, such that the first and second component nucleic acid molecules are collocated on the substrate. The system may include a finisher that dispenses a reaction mix onto the coordinate on the substrate to physically link the first and second component nucleic acid molecules, provides a condition necessary to physically link the first and second component nucleic acid molecules, or both.

Abstract: The structures and methods disclosed herein include changing composition of a metal alloy layer in an epitaxial electrode material to achieve tunable work functions for the electrode. In one example, the tunable work function is achieved using a layered structure, in which a crystalline rare earth oxide (REO) layer is epitaxially over a substrate or semiconductor, and a metal layer is over the crystalline REO layer. A semiconductor layer is thus in turn epitaxially grown over the metal layer, with a metal alloy layer over the semiconductor layer such that the ratio of constituents in the metal alloy is used to tune the work function of the metal layer.

Abstract: A semiconductor device includes a porous silicon layer on a silicon substrate. The semiconductor device also includes a seal layer on the porous silicon layer. The semiconductor device further includes a high charge carrier mobility material layer on the seal layer. The semiconductor device may further include a strain balancing intermediate layer between the seal layer and the high charge carrier mobility material layer. Different high charge carrier mobility materials can be used in the high charge carrier mobility material layer to form different semiconductor devices.

Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.

Abstract: A semiconductor device includes a porous silicon layer on a silicon substrate. A strain inducing intermediate layer (SIIL) is on the porous silicon layer. A silicon layer is on the SIIL. Lattice constant of the silicon layer is different from lattice constant of the SIIL. Thus, the silicon layer is strained. By employing different strain inducing materials in the SIIL, the silicon layer can be used to form different complementary metal oxide semiconductor (CMOS) transistors with improved characteristics.

Abstract: The structures and methods disclosed herein include changing composition of a metal alloy layer in an epitaxial electrode material to achieve tunable work functions for the electrode. In one example, the tunable work function is achieved using a layered structure, in which a crystalline rare earth oxide (REO) layer is epitaxially over a substrate or semiconductor, and a metal layer is over the crystalline REO layer. A semiconductor layer is thus in turn epitaxially grown over the metal layer, with a metal alloy layer over the semiconductor layer such that the ratio of constituents in the metal alloy is used to tune the work function of the metal layer.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

Abstract: A semiconductor on insulator (SOI) device may include a semiconductor handle substrate. The semiconductor hand may include a porous semiconductor layer, and an etch stop layer proximate the porous semiconductor layer. The SOI may also include an insulator layer on the etch stop layer. The SOI may further include a device semiconductor layer on the insulator layer.

Abstract: A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer. The method may further include back grinding a rear surface of the semiconductor wafer to expose the porous silicon layer along the outline of the dies. The method also includes etching the semiconductor wafer to release the dies.

Abstract: An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.

Abstract: A device is provided for correlating at least one noisy analog signal which is one of a plurality of signals obtained by a plurality of receivers. The device comprises a 1-bit quantization element to which is supplied, in use, the noisy signal; a comparator configured to compare the quantized signal with a reference signal which is a consensus signal obtained by averaging data from the plurality of receivers; and an up/down counter that is configured to be incremented by a subset of the comparison signal.

Abstract: A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.