Patents by Inventor Richard Hammond

Richard Hammond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7838392
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: November 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Publication number: 20100264995
    Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.
    Type: Application
    Filed: April 26, 2010
    Publication date: October 21, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Glyn Braithwaite, Richard Hammond, Matthew Currie
  • Publication number: 20100256453
    Abstract: A surgical access portal includes a seal housing and a sleeve mounted to the sleeve housing having an internal longitudinal passage adapted to provide access to underlying tissue. A seal is in mechanical cooperation with an inner wall of the seal housing and has an opening for reception and passage of a surgical instrument in a substantially sealed relation. A sponge is disposed distally of the seal and absorbs fluids that enter the seal housing.
    Type: Application
    Filed: March 4, 2010
    Publication date: October 7, 2010
    Inventors: Richard Hammond, Sally Carter
  • Publication number: 20100241081
    Abstract: A surgical access device includes a housing; an access member extending distally from the housing and being dimensioned for positioning within tissue, and defining a longitudinal axis; and a seal assembly disposed within the housing. The seal assembly includes first and second seal components respectively having first and second seal members. Each of the first and second seal members defines a passage for passage of a surgical object in substantial sealed relation therewith. The first and second seal components are capable of relative rotation about the longitudinal axis between a first position, in which passages of the first and second seal members are in substantial alignment, and a second position where the passages of the first and second seal members are offset to inhibit the communication of fluid through the seal assembly.
    Type: Application
    Filed: February 16, 2010
    Publication date: September 23, 2010
    Inventor: Richard Hammond
  • Patent number: 7776697
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: August 17, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Patent number: 7709828
    Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: May 4, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Glyn Braithwaite, Richard Hammond, Matthew Currie
  • Publication number: 20090275963
    Abstract: First and second yarns are interconnected to form surgical devices. The first yarns include a plurality of filaments including one or more filaments made from a high strength material and the second yarns include a plurality of filaments including one or more filaments made from an absorbable material.
    Type: Application
    Filed: April 29, 2009
    Publication date: November 5, 2009
    Inventors: Thomas C. May, Joseph Hotter, Jon Reinprecht, Richard Hammond
  • Patent number: 7588994
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: September 15, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 7425751
    Abstract: A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiGe substrate and growing a liner oxide by wet oxidation such that oxidation is selective to SiGe only, with negligible oxidation of silicon surfaces. Selective oxidation results in oxide encroachment under strained-Si, thereby reducing the junction area after device fabrication is completed. Reduced junction area leads to reduced n+/p or p+/n junction leakage current.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: September 16, 2008
    Assignee: Agency for Science, Technology and Research
    Inventors: Narayanan Balasubramanian, Richard Hammond
  • Patent number: 7420201
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: September 2, 2008
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 7414259
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: August 19, 2008
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Publication number: 20080128751
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Application
    Filed: November 20, 2007
    Publication date: June 5, 2008
    Applicant: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Publication number: 20070293003
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Application
    Filed: August 30, 2007
    Publication date: December 20, 2007
    Inventors: Matthew Currie, Anthony Lochtefeld, Richard Hammond, Eugene Fitzgerald
  • Publication number: 20070293009
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Application
    Filed: August 31, 2007
    Publication date: December 20, 2007
    Inventors: Matthew Currie, Anthony Lochtefeld, Richard Hammond, Eugene Fitzgerald
  • Patent number: 7297612
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: November 20, 2007
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 7259388
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: August 21, 2007
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 7217603
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: May 15, 2007
    Assignee: AmberWave Systems Corporation
    Inventors: Matthew T. Currie, Richard Hammond
  • Patent number: 7217668
    Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: May 15, 2007
    Assignee: AmberWave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Richard Hammond, Matthew Currie
  • Publication number: 20070082470
    Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1?xGex layer on a substrate, a strained channel layer on the relaxed Si1?xGex layer, and a Si1?yGey layer; removing the Si1?yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
    Type: Application
    Filed: September 13, 2006
    Publication date: April 12, 2007
    Applicant: AmberWave System Corporation
    Inventors: Eugene Fitzgerald, Richard Hammond, Matthew Currie
  • Patent number: 7109516
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: September 19, 2006
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Glyn Braithwaite, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald