Patents by Inventor Richard Hammond

Richard Hammond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180076137
    Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.
    Type: Application
    Filed: November 8, 2017
    Publication date: March 15, 2018
    Inventors: Sinan GOKTEPELI, Plamen Vassilev KOLEV, Michael Andrew STUBER, Richard HAMMOND, Shiqun GU, Steve FANELLI
  • Patent number: 9917714
    Abstract: Apparatus (100) is described comprising: an antenna array (1021 . . . 102N); a plurality of units (1041 . . . 104N), each unit configured to mix a radio frequency signal from one or more of the antennas (102) with oscillating signals having phases defined by a global signal and to provide in-phase and quadrature-phase signals; a constellation rotation system configured to, for each unit, rotate a constellation point associated with the in-phase and quadrature-phase signals by a rotation angle to provide adjusted in-phase and quadrature-phase signals; signal buses (106, 107) for global in-phase and quadrature-phase signals configured to receive the adjusted in-phase and quadrature-phase signals, respectively, from a plurality of the units; a feedback system configured to, for each unit, compare one or more of the adjusted in-phase and quadrature-phase signals with one or more of the global in-phase and quadrature-phase signals to determine an error in the rotation angle.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: March 13, 2018
    Assignee: Phasor Solutions Limited
    Inventor: Richard Hammond Mayo
  • Publication number: 20180069079
    Abstract: In a particular aspect, a device includes a substrate including a first trap rich layer region and a second trap rich layer region. The first trap rich layer region is separated from the second trap rich layer region by a portion of the substrate. The device further includes a semiconductor device layer including one or more components.
    Type: Application
    Filed: September 2, 2016
    Publication date: March 8, 2018
    Inventors: Steve Fanelli, Richard Hammond
  • Publication number: 20180068886
    Abstract: An integrated radio frequency (RF) circuit structure may include an active device on a front-side surface of a semiconductor device layer. A backside surface opposite the front-side surface of the semiconductor device layer may be supported by a backside dielectric layer. The integrated RF circuit structure may also include a handle substrate on a front-side dielectric layer that is on a front-side of the active device and a least a portion of the front-side surface of the semiconductor device layer. The integrated RF circuit structure may further include the backside dielectric layer on the backside surface of the semiconductor device layer. The backside dielectric layer may be arranged distal from the front-side dielectric layer.
    Type: Application
    Filed: September 2, 2016
    Publication date: March 8, 2018
    Inventors: Richard HAMMOND, Sinan GOKTEPELI
  • Publication number: 20180053852
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Application
    Filed: October 16, 2017
    Publication date: February 22, 2018
    Inventors: Matthew T. Currie, Richard Hammond
  • Patent number: 9847293
    Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: December 19, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Plamen Vassilev Kolev, Michael Andrew Stuber, Richard Hammond, Shiqun Gu, Steve Fanelli
  • Patent number: 9833240
    Abstract: A system for closing an aperture in a biological tissue includes at least one clip connected to at least one frame arm and for releasably retaining a surgical implant to the frame arm. The clip includes at least one locking structure for engaging a lock bar. A portion of the lock bar selectively engages or contacts the locking structure of the at least one clip to lock the at least one clip in a closed position by inhibiting rotation of the at least one clip when the lock bar is in a locked position. The lock bar allows the at least one clip to rotate to an open position when the lock bar is in an unlocked position. Methods for utilizing the system are also disclosed.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: December 5, 2017
    Assignee: Covidien LP
    Inventors: Jonathan Glick, Richard Hammond, Ofek Levin, Arie Levy
  • Patent number: 9812572
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Richard Hammond
  • Publication number: 20170288715
    Abstract: A device is provided for correlating at least one noisy analogue signal which is one of a plurality of signals obtained by a plurality of receivers. The device comprises a 1-bit quantisation element to which is supplied, in use, the noisy signal; a comparator configured to compare the quantised signal with a reference signal which is a consensus signal obtained by averaging data from the plurality of receivers; and an up/down counter that is configured to be incremented by a subset of the comparison signal.
    Type: Application
    Filed: April 14, 2017
    Publication date: October 5, 2017
    Inventor: Richard Hammond Mayo
  • Patent number: 9780210
    Abstract: An integrated circuit structure may include a transistor on a front-side semiconductor layer supported by an isolation layer. The transistor is a first source/drain/body region. The integrated circuit structure may also include a raised source/drain/body region coupled to a backside of the first source/drain/body region of the transistor. The transistor is a raised source/drain/body region extending from the backside of the first source/drain/body region toward a backside dielectric layer supporting the isolation layer. The integrated circuit structure may further include a backside metallization coupled to the raised source/drain/body region.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: October 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Richard Hammond
  • Publication number: 20170179285
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
  • Publication number: 20170117176
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Application
    Filed: January 6, 2017
    Publication date: April 27, 2017
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 9628125
    Abstract: A device is provided for correlating at least one noisy analog signal which is one of a plurality of signals obtained by a plurality of receivers. The device comprises a 1-bit quantization element to which the noisy signal is supplied; a comparator configured to compare the quantized signal with a reference signal which is a consensus signal obtained by averaging data from the plurality of receivers; and an up/down counter that is configured to be incremented by a subset of the comparison signal.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: April 18, 2017
    Assignee: Phasor Solutions Limited
    Inventor: Richard Hammond Mayo
  • Patent number: 9601623
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
  • Publication number: 20170063585
    Abstract: Apparatus (100) is described comprising: an antenna array (1021 . . . 102N); a plurality of units (1041 . . . 104N), each unit configured to mix a radio frequency signal from one or more of the antennas (102) with oscillating signals having phases defined by a global signal and to provide in-phase and quadrature-phase signals; a constellation rotation system configured to, for each unit, rotate a constellation point associated with the in-phase and quadrature-phase signals by a rotation angle to provide adjusted in-phase and quadrature-phase signals; signal buses (106, 107) for global in-phase and quadrature-phase signals configured to receive the adjusted in-phase and quadrature-phase signals, respectively, from a plurality of the units; a feedback system configured to, for each unit, compare one or more of the adjusted in-phase and quadrature-phase signals with one or more of the global in-phase and quadrature-phase signals to determine an error in the rotation angle.
    Type: Application
    Filed: February 25, 2015
    Publication date: March 2, 2017
    Inventor: Richard Hammond Mayo
  • Patent number: 9548236
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: January 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Publication number: 20160300729
    Abstract: Methods and apparatus for passivation of semiconductor interfaces by deuterium annealing are described. Harmonic improvements after deuterium annealing of a SOI semiconductor device with a trap-rich layer was demonstrated. Secondary ion mass spectroscopy after deuterium anneal shows a deuterium rich interface layer at the BOX-trap-rich layer interface of a MOSFET semiconductor device.
    Type: Application
    Filed: April 10, 2015
    Publication date: October 13, 2016
    Inventors: Sinan Goktepeli, Richard Hammond
  • Publication number: 20160240676
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Application
    Filed: April 25, 2016
    Publication date: August 18, 2016
    Inventors: Matthew T. Currie, Richard Hammond
  • Publication number: 20160190254
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Patent number: 9372051
    Abstract: A rifle scope includes at least one optical sensor configured to capture optical data corresponding to at least one of a barrel of a firearm and an appendage coupled to the barrel. The rifle scope further includes a controller coupled to the at least one optical sensor and configured to determine an angular position of the barrel in response to capturing the optical data. The controller is configured to automatically determine an alignment of the rifle scope relative to the barrel in response to determining the angular position.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: June 21, 2016
    Assignee: TrackingPoint, Inc.
    Inventors: Matthew Flint Kepler, Douglas Richard Hammond